參數(shù)資料
型號(hào)： STSAM9708
廠商： Atmel Corp.
英文描述： Sound Synthesis
中文描述： 聲音合成
文件頁(yè)數(shù)： 13/30頁(yè)
文件大小： 373K
代理商： STSAM9708
13
ATSAM9708
1772D–DRMSD–01/04
External Memory Timing
External Memory
Overview
The following memories can be connected to the ATSAM9708:
ROM or Flash memories, 16 bits wide
Static RAMs, 8 bits or 16 bits wide
DRAMs, 16 bits wide
SDRAMs, 16 bits wide
DRAMs and SDRAMs cannot be connected at the same time. The type of dynamic RAM
connection is determined at power-up by sensing the level of pins RAS and CAS (see
Table 4 on page 4 and “Memory Type Configuration and Boot Configuration” on page
26).
Eight-bit wide static RAM can be connected using the additional Ram Byte Select (RBS)
address signal. RBS allows access to two bytes of SRAM within one regular memory
cycle, thereby providing 16 bits of data. Eight-bit wide SRAM can be connected only
under control of WCS1. The selection 8 bits/16 bits is done by firmware.
ROM and static RAMs use linear addressing (address lines WA0 to WA26). DRAM and
SDRAMs use time-multiplexed addressing with a ROW/COL scheme (address lines
DRA0 to DRA11). Additionally, SDRAMs use the DRA0/DRA11 lines for configuration
and the DRA10 line for auto precharge.
ROM/SRAMs and DRAM/SDRAM address line share the same pins of the ATSAM9708.
The timing is determined by the input signal DRAM. If DRAM is high at the beginning of
a memory cycle, this indicates DRAM/SDRAM access.
If only one type of memory is connected (i.e., SDRAM), then the DRAM signal can be
hardwired. Otherwise, it should be derived from an external decoding of high-order
address lines.
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