參數(shù)資料
型號: STSAM9708
廠商: Atmel Corp.
英文描述: Sound Synthesis
中文描述: 聲音合成
文件頁數(shù): 22/30頁
文件大小: 373K
代理商: STSAM9708
22
ATSAM9708
1772D–DRMSD–01/04
Figure 16.
8-bit SRAM Write Cycle
t
WC
t
CSWE
t
WP
WA[26:0]
WD[7:0]
WCS1
WOE
WWE
LOW
HIGH
RBS
t
WP
t
AS
t
DW1
t
DH1
t
DW2
t
DH2
Table 15.
External 8-bit SRAM Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
t
RC
Word (2 x bytes) read cycle time
6 x t
CK
ns
t
CSOE
Chip select low/address valid to WOE low
t
CK
ns
t
POE
Output enable pulse width
5 x t
CK
ns
t
ACE
Chip select/address low byte access time
3 x t
CK
- 5
ns
t
OE
Output enable low byte access time
2 x t
CK
- 5
ns
t
ORB
Output enable low to byte select high
2 x t
CK
ns
t
ACH
Byte select high byte access time
3 x t
CK
- 5
ns
t
DF
Chip select or WOE high to input data
High Z
0
t
CK
- 5
ns
t
WC
Word (2 x bytes) write cycle time
6 x t
CK
ns
t
CSWE
1st WWE low from CS or Address or WOE
t
ck
- 10
ns
t
WP
Write (low and high byte) pulse width
1.5 x t
CK
ns
t
DW1
Data out low byte setup time
1.5 x t
CK
- 10
ns
t
DH1
Data out low byte hold time
10
ns
t
AS
RBS high to second write pulse
t
CK
- 5
ns
t
DW2
Data out high byte setup time
2.5 x t
CK
- 10
ns
t
DH2
Data out high byte hold time
10
ns
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