參數(shù)資料
型號(hào): STP1081ABGA-125
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA256
封裝: PLASTIC, BGA-256
文件頁(yè)數(shù): 4/32頁(yè)
文件大?。?/td> 478K
代理商: STP1081ABGA-125
12
STP1081
Preliminary
Companion Device for 250/300 MHz UltraSPARC-II Systems
UltraSPARC
-II Data Buffer (UDB-II)
July 1997
TDO
O
JTAG Interface. IEEE standard 1149 test data output. A three-state signal driven only when
that TAP controller is in the shift-DR state.
TMS
I
IEEE standard 1149 test mode select input. This pin is internally pulled to logic 1 when not
driven.
TCK
I
IEEE standard 1149 test clock input. If not hooked to a clock source, this pin must always
be driven to a logic 1 or a logic 0.
TRST_L
I
IEEE standard 1149 test reset input (active low). This pin is internally pulled to logic 1 when
not driven.
DATA_STALL
I
Input from the UPA bus to indicate the data is delayed.
ECC_VALID
I
Input from the UPA to indicate when to ignore ECC of SYSDATA coming in from the UPA
bus. When this value is one, UDB-II generates ECC from SYSDATA and compares it with
incoming ECC. If there is a mismatch, UDB-II attempts to correct the data, it then updates
CE and UE (see the explanations earlier in this table). When this signal is zero, the data
from the UPA bus is not checked for errors.
LF1A
I
SYSCLK PLL loop lter input of charge pump.
LF2A
I
SYSCLK PLL loop lter input pin to VCO.
LF3A
I
SYSCLK Loop lter ground.
LF1B
I
EBUS_CLK PLL loop lter input of charge pump.
LF2B
I
EBUS_CLK PLL loop lter input pin to VCO.
LF3B
I
EBUS_CLK Loop lter ground.
SYS_CLKOUT
O
Output of the internal (SYSCLK) clock for characterization of clock in PLL or BYPASS
mode.
EBUS_CLKOUT
O
Output of the internal (EBUS_CLK) clock for characterization of clock in PLL or BYPASS
mode.
SIGNAL DESCRIPTIONS (CONTINUED)
Symbol
Type
Name and Function
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