參數(shù)資料
型號(hào)： STP1100BGA-100
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 100 MHz, RISC PROCESSOR, PBGA272
封裝： PLASTIC, BGA-272
文件頁(yè)數(shù)： 1/32頁(yè)
文件大?。?/td> 168K
代理商： STP1100BGA-100
Preliminary
DATA SHEET
1
STP1100BGA
microSPARC-IIep
SPARC v8 32-Bit Microprocessor With PCI/DRAM Interfaces
DESCRIPTION
The microSPARC-IIep 32-bit microprocessor is a highly integrated, high-performance microprocessor. Imple-
menting the SPARC Architecture version 8 specication, it is ideally suited for low-cost uniprocessor
embedded applications.
It is built with leading edge CMOS technology, with the core operating at a low voltage of 3.3V for optimized
power consumption.
The microSPARC-IIep includes on chip: integer unit (IU), oating-point unit (FPU), large separate instruction
and data caches, a 32-entry version 8 reference MMU, programmable DRAM controller, PCI controller, PCI
bus interface, a 16-entry IOMMU, ash memory interface support, interrupt controller, 2 timers, internal and
boundary scan through JTAG interface, power management and clock generation capabilities.
The operating frequencies are 100 MHz.
Features
Benets
Integrated 32-bit, 33 MHz PCI expansion bus controller
Connection to industry-standard expansion bus
Integrated 256 MByte DRAM controller
High-bandwidth memory controller to reduce latency
Built-in 16 MByte ash memory controller
Flash memory interface runs real-time operating systems
that loads and runs code out of ROM
SPARC high-performance RISC architecture
Compatible with over 10,000 applications and existing
development tools
Support for little and big endian byte ordering
Handles with ease PCI devices designed for DOS
machines, along with UNIX applications
8-window, 136-word register le
Fast interrupt response, procedure calls, and program
execution
16 KByte instruction cache and 8 KByte data cache
Decouples processor operation from slow external memory
Built-in oating-point unit
Supports concurrent execution of oating-point and integer
instructions
On-chip memory management unit
Support for sophisticated operating systems with memory
protection and virtual addressing
Operating voltage of 3.3V with 5V compatible I/O
Low-power core reduces power consumption and supports
industry-standard peripherals
Integrated power management circuitry
Consumes minimal power during standby
IEEE 1149.1 (JTAG) boundary scan test bus
Ease of manufacturing tests
December 1997
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