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參數(shù)資料
| 型號(hào)： | STP1100BGA-100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 23/32頁(yè) |
| 文件大小： | 168K |
| 代理商： | STP1100BGA-100 |
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3
SPARC v8 32-Bit Microprocessor With PCI/DRAM Interfaces
microSPARC-IIep
STP1100BGA
Preliminary
December 1997
Sun Microsystems, Inc
TECHNICAL OVERVIEW
Integer Unit (IU)
The microSPARC-IIep integer unit executes SPARC integer instructions dened in the SPARC Architecture
Manual version 8. The IU contains 136 registers supporting 8-window registers and 8-global registers. It has
numerous high performance features include instruction prefetching, branch folding and 5-stage instruction
pipeline. The IU supports little- and big-endian byte ordering of data.
Floating-Point Unit (FPU)
The oating-point unit executes all single- and double-precision oating-point instructions dened in the
SPARC Architecture Manual version 8. The FPU traps on quad-precision instructions and transfers their exe-
cution to software. The FPU contains a oating-point core based on Meiko design, a fast-multiplier, a
3-instruction deep instruction queue, and 32 32-bit oating-point registers. The oating-point core and fast
multiplier allow parallel execution of oating multiplication (FPMUL) and another oating-point instruction
while the instruction queue support concurrent execution of oating-point and integer instruction.
Memory Management Unit (MMU)
The microSPARC-IIep memory management unit translates 32-bit virtual addresses to 31-bit physical
address. It maps physical address into 8 different address spaces. The MMU provides functionalities specied
in the SPARC version 8 Reference MMU and implements hardware table-walk. It implements a 32-entry
fully-associative translation lookaside buffer (TLB) and provides memory protection for 256 contexts.
Instruction Cache
The instruction cache is a 16 KByte, direct-mapped, virtually-indexed, virtually-tagged cache. The instruction
cache is organized as 512 lines of 32 bytes plus 32 tag bits. To reduce read-miss latency, the instruction cache
supports cache rell in two 32-bit words, streaming and bypass.
Data Cache
The data cache is an 8-KByte, direct-mapped, virtually-indexed, virtually-tagged cache. Cache write policy
supported is write-through with no write-allocate. The data cache is organized as 512 lines of 16 bytes plus 32
tag bits. The data cache provides zero-penalty data accesses for cache hits.
To reduce write latency, the data cache contains a 4-deep double-word store buffer. To reduce read-miss
latency, the data cache supports cache rell in two 32-bit words, streaming and bypass.
DRAM Interface
The microSPARC-IIep DRAM interface supports industry standard fast-page mode DRAM and EDO DRAM
that support fast-page mode. It supports 8 banks of memory up to a total of 256 MBytes of system memory.
Each bank of memory can be consisted of 8 MBytes, 16 MBytes or 32 MBytes. The DRAM interface is pro-
grammable and support different memory speeds relative to the processor frequency.
The DRAM data bus is 64 bits wide with two parity bits, each covering 32-bits of data. The parity bits can be
disabled.
The DRAM interface provides a programmable DRAM refresh controller that supports CAS-before-RAS
refresh.
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