參數(shù)資料
型號(hào)： STP1081ABGA-125
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA256
封裝： PLASTIC, BGA-256
文件頁(yè)數(shù)： 30/32頁(yè)
文件大?。?/td> 478K
代理商： STP1081ABGA-125
7
Companion Device for 250/300 MHz UltraSPARC-II Systems
UltraSPARC
-II Data Buffer (UDB-II)
STP1081
Preliminary
July 1997
When an ECC error occurs at the same time as the UDB-II status register is being written by software, the syn-
drome is updated according to the UE and CE bits with the software clearing factored in. This is consistent
with the conceptual model of software update being performed before the error is logged.
Assertion of ECC_VALID (same cycle as S_REPLY) indicates that the ECC bits accompanying the data being
driven are valid. Error detection and correction are disabled for incoming data when ECC_VALID is
deasserted.
Interrupts
The Data Path has storage for receiving mondo vectors. They reside in the UDB-II until Ultra-SPARC-II
retrieves them. UDB-II has the “real” mondo-vector registers that are visible to software.
Mondo-Vector Buffers
Interrupts are delivered as write transactions from the system controller to UltraSPARC-II. The interrupt is
signalled by a “mondo vector,” which is a group of three 64-bit packets. I/O devices interrupt by sending
mondo vector packets to a selected processor. The packet typically consists of one 64-bit PC, one 64-bit data
structure pointer, and one 64-bit piece of data.
UltraSPARC-II receives the mondo-vector. The processor can post interrupts to itself at any level by writing to
the SOFTINT register. SOFTINT register interrupts should not originate externally on the UPA, since the pro-
cessor will not be able to recognize or respond correctly to them.
Parity and ECC errors on reads are reported back to the LSU, which logs the error status and traps the proces-
sor. Errors on writes are reported asynchronously by slaves using mondo vectors.
Mondo-Send Unit
UltraSPARC-II can also send mondo vectors. This begins by ASI stores loading data into a special UDB-II
buffer. A nal ASI store initiates the mondo send. A status register in UltraSPARC-II can be read with an ASI
load to interrogate the completion status of such a mondo send.
Control and Data Transfers
The UDB-II has 64-byte buffers reserved for each request class except master writes. The noncacheable store
queue has eight (16-byte) entries to handle multiple noncacheable stores to the frame buffer. Data transfers
occur at some arbitrary time after address requests are made. Masters are responsible for buffering all data
associated with queued requests.
Mondo vector data delivery is handled as a normal system controller write.
The E-Cache bus is controlled by the UltraSPARC-II ECU. Besides E-Cache reads and writes, there are trans-
fers to and from the UDB-II. CNTL[4:0] provides the status of E-Cache bus to UDB-II.
TABLE 3: Mondo Vector Format
Component
Mondo_0
(Cycle 1)
Mondo_1
(Cycle 2)
Mondo_2
(Cycle 3)
Mondo_3
(Cycle 4)
UDB_H
Data0
Data1
Data2
-
UDB_L
----
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