參數(shù)資料
型號： STP1081ABGA-125
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA256
封裝： PLASTIC, BGA-256
文件頁數(shù)： 29/32頁
文件大?。?/td> 478K
代理商： STP1081ABGA-125
6
STP1081
Preliminary
Companion Device for 250/300 MHz UltraSPARC-II Systems
UltraSPARC
-II Data Buffer (UDB-II)
July 1997
Bad parity errors are not forced by the UDB-II; UltraSPARC-II writes the SRAMs with bad parity and the
UDB-II detects it. Bad ECC errors are forced in using the check bit vector FCBV[7:0] in each UDB microchip.
Operation of Error Detection and Correction
Parity Errors
If an E-Cache parity error occurs during a snoop, a known bad ECC data/checkbit pattern is forced. This
causes an uncorrectable error (UE) trap at the master that requested the data. The slave processor will log
error information (physical address and so on). This error log can be read by the master after trapping. The
slave is not interrupted.
If the E-Cache was being read for a writeback (victimized line), bad ECC is also generated before the data
goes to memory. In this case, the bad ECC guarantees no other processor will use the bad data. The error
information is logged in the same register, and the processor traps. Software can clean up the bad ECC in
memory in the trap handler.
ECC Errors
The UDB-II will not stall the data delivery to UltraSPARC-II on a correctable or uncorrectable error. Uncor-
rectable errors have bad parity forced, before the data is transferred to the E-Cache. This prevents the bad data
from being used or written to memory with correct check bits later on. In either case, the error log will save
the appropriate state. Separate CE and UE enables control whether the processor is trapped or not.
If the error occurs in a sub-block subsequent to one referenced by the processor, the trap will still occur.
If an ECC error is detected, bad parity is generated for the outgoing data either to UltraSPARC-II or to the
SRAM, or both.
1. This register is cleared to 0 at power-on reset; W1C implies write-1-to-clear.
TABLE 1: ECC Status Denition
[1]
Field
Description
Type
CE
Correctable Error
W1C
UE
Uncorrectable Error
W1C
E_Syndrome
ECC syndrome bits, 64 bits -> 8 bits
R
TABLE 2: ECC Control and Diagnostic Register Denition
Field
Description
Type
Version
Software-accessible version number, (TAP_IDreg[31:28])
R
FMODE
Force check bit vector for data to UPA
RW
FCBV
Forced check bit vector
RW
Reserved
Figure 5. ECC Control and Diagnostic Register (Duplicated in UDB_H and UDB_L)
Version[3:0]
FMODE
FCBV[7:0]
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