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參數(shù)資料
| 型號： | STA323WTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2.1 HIGH EFFICIENCY DIGITAL AUDIO SYSTEM |
| 中文描述： | 2.1高效率數(shù)字音頻系統(tǒng) |
| 文件頁數(shù)： | 9/41頁 |
| 文件大?。?/td> | 749K |
| 代理商： | STA323WTR |
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STA323W
6.1 COMMUNICATION PROTOCOL
6.1.1 Data Transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock
is high is used to identify a START or STOP condition.
6.1.2 Start Condition
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is
stable in the high state. A START condition must precede any command for data transfer.
6.1.3 Stop Condition
STOP is identified by a low to high transition of the data bus SDA signal while the clock signal SCL is stable
in the high state. A STOP condition terminates communication between STA323W and the bus master.
6.1.4 Data Input
During the data input the STA323W samples the SDA signal on the rising edge of clock SCL. For correct
device operation the SDA signal must be stable during the rising edge of the clock and the data can
change only when the SCL line is low.
6.2 DEVICE ADDRESSING
To start communication between the master and the STA323W, the master must initiate with a start con-
dition. Following this, the master sends 8-bits (MSB first) onto the SDA line corresponding to the device
select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In
the STA323W the I2C interface uses a device addresse of 0x34 or 0011010x.
The 8th bit (LSB) identifies read or write operation, RW. This bit is set to 1 in read mode and 0 for write
mode. After a START condition the STA323W identifies the device address on the bus. If a match is
found, it acknowledges the identification on the SDA bus during the 9th bit time. The byte following the
device identification byte is the internal space address.
6.3 WRITE OPERATION
Following the START condition the master sends a device select code with the RW bit set to 0. The
STA323W acknowledges this and then the master writes the internal address byte.
After receiving the internal byte address the STA323W again responds with an acknowledgement.
6.3.1 Byte Write
In the byte write mode the master sends one data byte. This is acknowledged by the STA323W. The
master then terminates the transfer by generating a STOP condition.
6.3.2 Multi-byte Write
The multi-byte write modes can start from any internal address. Sequential data byte writes will be written
to sequential addresses within the STA323W.
The master generating a STOP condition terminates the transfer.
6.4 READ OPERATION
6.4.1 Current Address Byte Read
Following the START condition the master sends a device select code with the RW bit set to 1. The
STA323W acknowledges this and then responds by sending one byte of data. The master then terminates
the transfer by generating a STOP condition.
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