參數(shù)資料
型號: STA323WTR
廠商: 意法半導(dǎo)體
英文描述: 2.1 HIGH EFFICIENCY DIGITAL AUDIO SYSTEM
中文描述: 2.1高效率數(shù)字音頻系統(tǒng)
文件頁數(shù): 26/41頁
文件大小: 749K
代理商: STA323WTR
STA323W
26/41
7.10Channel Configuration Registers
7.10.1Channel 1 Configuration (Address 0Eh)
7.10.2Channel 2 Configuration (Address 0Fh)
7.10.3Channel 3 Configuration (Address 10h)
EQ control can be bypassed on a per channel basis. If EQ control is bypassed on a given channel the
prescale and all 9 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in
any combination) are bypassed for that channel.
CxEQBP:
– 0 Perform EQ on Channel X – normal operation
– 1 Bypass EQ on Channel X
Tone control (bass/treble) can be bypassed on a per channel basis. If tone control is bypassed on a given
channel the two filters that tone control utilizes are bypassed.
CxTCB:
– 0 Perform Tone Control on Channel x – (default operation)
– 1 Bypass Tone Control on Channel x
Each channel can be configured to output either the patented DDX PWM data or standart binary PWM
encoded data. By setting the CxBO bit to ‘1’, each channel can be individually controlled to be in binary
operation mode.
Also, there is the capability to map each channel independently onto any of the two limiters available within
the STA323W or even not map it to any limiter at all (default mode).
Table 24. Channel Limiter Mapping Selection
Each PWM Output Channel can receive data from any channel output of the volume block. Which channel
a particular PWM output receives is dependent upon that channel’s CxOM register bits.
D7
D6
D5
D4
D3
D2
D1
D0
C1OM1
C1OM0
C1LS1
C1LS0
C1BO
C1VBP
C1EQBP
C1TCB
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
C2OM1
C2OM0
C2LS1
C2LS0
C2BO
C2VBP
C2EQBP
C2TCB
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
C3OM1
C3OM0
C3LS1
C3LS0
C3BO
C3VBP
0
0
0
0
0
0
CxLS (1,0)
Channel Limiter Mapping
00
Channel has limiting disabled
01
Channel is mapped to limiter #1
10
Channel is mapped to limiter #2
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