參數(shù)資料
型號(hào)： STA323WTR
廠商： 意法半導(dǎo)體
英文描述： 2.1 HIGH EFFICIENCY DIGITAL AUDIO SYSTEM
中文描述： 2.1高效率數(shù)字音頻系統(tǒng)
文件頁(yè)數(shù)： 2/41頁(yè)
文件大?。?/td> 749K
代理商： STA323WTR
STA323W
2/41
ment of digital processing features. This includes up to 4 programmable 28-bit biquads (EQ) per channel,
and bass/treble tone control. Automodes enable a time-to-market advantage by substantially reducing
the amount of software development needed for certain functions. This includes Auto Volume loudness,
preset volume curves, preset EQ settings, etc. New advanced AM radio inerference reduction modes.
The serial audio data input interface accepts all possible formats, including the popular I
2
S format.
Three channels of DDX processing are provided. This high quality conversion from PCM audio to DDX's
patented tri-state PWM switching waveform provides over 100dB SNR and dynamic range.
3
ORDERING INFORMATION
Figure 2. Block Diagram
Figure 3. Channel Signal Flow Diagram through the Digital Core
3.1 EQ Processing
Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ processing block.
In this block, upto 4 user-defined Biquads can be appplied to each of the two channels.
Pre-scaling, dc-blocking high-pass, de-emphasis, bass, and tone control filters can also be applied based
on various configuration parameter settings.
The entire EQ block can be bypassed for all channels simulatneously by setting the DSPB bit to '1'. And
the CxEQBP bits can be used to bypass the EQ functionality on a per channel basis. Figure below shows
the internal signal flow through the EQ block.
Resampling
Processing
Power Stage
OUT1A
OUT1B
OUT2A
OUT2B
LRCKI
SDI_12
SDA
SCL
PLL
CLK
EAPD
BICKI
FAULT
TWARN
Power-Down
I
2
C
System Contro
l
Processing
System Timing
DDX-SPIRIT
Serial Data
Input,
Channel
Mapping &
DDX
Quad
Half-Bridge
Audio EQ, Mix,
Crossver,
Volume, Limiter
Channel
Mapping
Re-sampling
EQ
Processing
Mix
Volume
Limiter
4X
Interp
DDX
I
2
S
Input
DDX
Output
Crossover
Filter
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