參數(shù)資料
型號： STA323WTR
廠商： 意法半導(dǎo)體
英文描述： 2.1 HIGH EFFICIENCY DIGITAL AUDIO SYSTEM
中文描述： 2.1高效率數(shù)字音頻系統(tǒng)
文件頁數(shù)： 14/41頁
文件大?。?/td> 749K
代理商： STA323WTR
STA323W
14/41
7.3 Serial Data Interface
The STA323W serial audio input was designed to interface with standard digital audio components and to
accept a number of serial data formats. The STA323W always acts as a slave when receiving audio input
from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/
right clock LRCKI (pin 33), serial clock BICKI (pin 31), and serial data 1 & 2 SDI12 (pin 32).
The SAI register (Configuration Register B - 01h, Bits D3-D0) and the SAIFB register (Configuration Reg-
ister B - 01h, Bit D4) are used to specify the serial data format. The default serial data format is I2S, MSB-
First. Available formats are shown in Figure 11 and the tables that follow.
Figure 12. General Serial Input and Output Formats
For example, SAI=1110 and SAIFB=1 would specify Right-Justified 16-bit data, LSB-First.
Table 10 below lists the serial audio input formats supported by STA323W as related to BICKI = 32/48/
64fs, where the sampling rate fs = 32/44.1/48/88.2/96/176.4/192 kHz.
Table 9. First Bit Selection Table
Note: Serial input and output formats are specified distinctly.
SAIFB
Format
0
MSB-First
1
LSB-First
I
2
S
Left Justified
LRCLK
Left
Right
SCLK
SDATA
LSB
MSB
LSB
MSB
MSB
LRCLK
Left
Right
SCLK
SDATA
LSB
MSB
LSB
MSB
MSB
Right Justified
LRCLK
Left
Right
SCLK
SDATA
LSB
MSB
LSB
MSB
MSB
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