參數(shù)資料
型號(hào)： STA323WTR
廠商： 意法半導(dǎo)體
英文描述： 2.1 HIGH EFFICIENCY DIGITAL AUDIO SYSTEM
中文描述： 2.1高效率數(shù)字音頻系統(tǒng)
文件頁(yè)數(shù)： 8/41頁(yè)
文件大小： 749K
代理商： STA323WTR
STA323W
8/41
5
FUNCTIONAL DESCRIPTION
5.1 PIN DESCRIPTION
5.1.1 OUT1A, 1B, 2A & 2B (Pins 16, 10, 9 & 3)
Output Half Bridge PWM Outputs 1A, 1B, 2A & 2B provide the inputs signals to the speaker devices.
5.1.2 RESET (Pin 23)
Driving RESET low sets all outputs low and returns all register settings to their defaults. The reset is asyn-
chronous to the internal clock.
5.1.3 I
2
C Signals (Pins 24 & 25)
The SDA (I2C Data) and SCL (I2C Clock) pins operate per the I2C specification. See Section 4.0. Fast-
mode (400kB/sec) I2C communication is supported.
5.1.4 GNDA & VDDA: Phase Locked Loop Power (Pins 27-28)
The phase locked loop power is applied here. This +3.3V supply must be well bypassed and filtered for
noise immunity. The audio performance of the device is critically dependent upon the PLL circuit.
5.1.5 CLK: Master Clock In (Pin 29)
This is the master clock in required for the operation of the digital core. The master clock must be an in-
teger multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz (256*Fs) for
a 48kHz sample rate, which is the default at power-up. Care must be taken to avoid over-clocking the
device i.e provide the device with the nominally required system clock; otherwise, the device may not prop-
erly operate or be able to communicate.
5.1.6 FILTER_PLL: PLL Filter (Pin 30)
PLL Filter connects to external filter components for PLL loop compensation. Refer to the schematic dia-
gram for the recommended circuit.
5.1.7 BICKI: Bit Clock In (Pin 31)
The serial or bit clock input is for framing each data bit. The bit clock frequency is typically 64*Fs, for ex-
ample using I2S serial format.
5.1.8 SDI_12: Serial Data Input (Pin 32)
PCM audio information enters the device here. Six format choices are available including I2S, left- or right-
justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
5.1.9 LRCKI: Left/Right Clock In (Pin 33)
The Left/Right clock input is for data word framing. The clock frequency will be at the input sample rate Fs.
5.2 AUDIO PERFORMANCE
TBD
5.3 PIN CONNECTION (Top View)
6
The STA323W supports the I2C protocol. This protocol defines any device that sends data on to the bus
as a transmitter and any device that reads the data as a receiver. The device that controls the data trans-
fer is known as the master and the other as the slave. The master always starts the transfer and provides
the serial clock for synchronization. The STA323W is always a slave device in all of its communications.
STA323W I
2
C BUS SPECIFICATION
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