參數(shù)資料
型號(hào)： SN74V3690-15PEU
廠商： Texas Instruments, Inc.
英文描述： 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
中文描述： 的3.3V的CMOS先入先出存儲(chǔ)器
文件頁數(shù)： 7/50頁
文件大?。?/td> 729K
代理商： SN74V3690-15PEU
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024
×
36, 2048
×
36, 4096
×
36, 8192
×
36, 16384
×
36, 32768
×
36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A
–
NOVEMBER 2001
–
REVISED MARCH 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
REN
I
Read enable. REN enables RCLK for reading data from the FIFO memory and offset registers.
RM
I
Retransmit latency mode. During master reset, a low on RM selects zero-latency retransmit timing mode. A high on
RM selects normal-latency mode.
RT
I
Retransmit. RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to low (OR
to high in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode, or
programmable-flag settings. RT is useful to reread data from the first physical location of the FIFO.
SEN
I
Serial enable. SEN enables serial loading of programmable flag offsets.
WCLK
I
Write clock. When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programming and, when enabled by SEN, the rising edge of WCLK writes one bit
of data into the programmable register for serial programming.
WEN
Inputs should not change state after master reset.
I
Write enable. WEN enables WCLK for writing data into the FIFO memory and offset registers.
detailed description
inputs
data in (D0–Dn)
D0
–
D35 are data inputs for 36-bit-wide data. D0
–
D17 are data inputs for 18-bit-wide data. D0
–
D8 are data
inputs for 9-bit-wide data.
controls
master reset (MRS)
A master reset is accomplished when MRS is taken low. This operation sets the internal read and write pointers
to the first location of the RAM array. PAE goes low, PAF goes high, and HF goes high.
If FWFT/SI is low during master reset, the standard mode, EF, and FF are selected. EF goes low and FF goes
high. If FWFT/SI is high, the FWFT mode, IR, and OR are selected. OR goes high and IR goes low.
All control settings, such as OW, IW, BM, BE, RM, PFM, and IP are defined during the master reset cycle.
During a master reset, the output register is initialized to all zeroes. A master reset is required after power up,
before a write operation can take place. MRS is asynchronous.
See Figure 5 for timing information.
相關(guān)PDF資料
PDF描述
SN75108AN DUAL LINE RECEIVERS
SN55107AFK DUAL LINE RECEIVERS
SN55107AW DUAL LINE RECEIVERS
SN75109A 5K 20 TURN POTENTIOMETER
SN75109AD DUAL LINE DRIVERS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74V3690-6PEU 功能描述:先進(jìn)先出 32768 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74V3690-7PEU 功能描述:先進(jìn)先出 32768 x 36 Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74VLTH162244DLR 制造商:Texas Instruments 功能描述:
SN74VMEH22501ADGG 制造商:Texas Instruments 功能描述:
SN74VMEH22501ADGGR 功能描述:通用總線函數(shù) 8-Bit Univ & 2 1-Bit Bus Trncvr W/3St Otp RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*