參數(shù)資料
型號(hào): SN74V3690-15PEU
廠商: Texas Instruments, Inc.
英文描述: 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
中文描述: 的3.3V的CMOS先入先出存儲(chǔ)器
文件頁(yè)數(shù): 34/50頁(yè)
文件大小: 729K
代理商: SN74V3690-15PEU
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024
×
36, 2048
×
36, 4096
×
36, 8192
×
36, 16384
×
36, 32768
×
36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A
NOVEMBER 2001
REVISED MARCH 2003
34
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
tENS
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
1
2
1
2
WEN
3
4
tENS
tENH
tRTS
tENH
tA
tA
tsk2
tENS
tENH
tREF
tREF
tPAES
tHF
Q0
Qn
Wx
Wx + 1
W4
tPAFS
tRTS
tA
tA
W1 (see Note D)
W2 (see Note D)
W3 (see Note D)
NOTES: A. Retransmit setup is complete after OR returns low.
B. No more than (D
2) words can be written to the FIFO between reset (master or partial) and retransmit setup. Therefore, IR is
low throughout the retransmit setup procedure.
D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the SN74V3660, D = 8193 for the SN74V3670, D = 16385
for the SN74V3680, and D = 32769 for the SN74V3690.
C. OE = low
D. W1, W2, W3 = first, second, and third words written to the FIFO after master reset
E. There must be at least two words written to the FIFO before a retransmit operation can be invoked.
F. RM is set high during MRS.
Figure 9. Retransmit Timing (FWFT Mode)
P
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