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參數(shù)資料
| 型號： | SM3-19.44M |
| 廠商： | Connor-Winfield |
| 文件頁數(shù)： | 7/36頁 |
| 文件大小： | 0K |
| 描述： | IC MOD TIMING 19.440MHZ STATUM 3 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SM3 |
| 類型： | 定時(shí)模塊，系統(tǒng)時(shí)鐘 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，ADM，DSLAM，SONET/SDH，Stratum，TDM |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 19.44MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-DIP 模塊 |
| 包裝： | 管件 |
| 其它名稱： | CW642 SM3 19.44M SM319.44M |
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SM3 Data Sheet #:
TM052
Page 15 of 36 Rev: 06 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Register Descriptions and Operation continued
*NOTE: Only references 1 - 4 are used with this model
Phase_Offset, 0x0e (R/W)
Bit 7 ~ Bit 0
The2’scomplementvalueofphaseoffsetbetweenMasterOutputmoduleandSlaveOutputmodule,rangesfrom-32nSto+31.75nS
PositiveValue:MasterOutputrisingedgeleadsSlaveOutput
NegativeValue:MasterOutputrisingedgelagsSlaveOutput
In slave mode, the slave’s outputs may be phase shifted -32nS to +31.75nS in .25nS increments, relative to the Master
module according to the contents of the
Phase_Offset register, to compensate for the path length of the Master to Slave
connection.
If a phase offset is used, then the two SM3 devices would typically be written to the appropriate phase offset values for
the respective path lengths of each Master to Slave connection, to ensure that the same relative output signal phases
will persist through master/slave switches.
Calibration, 0x0f (R/W)
Bit 7 ~ Bit 0
2’scomplementvalueoflocaloscillatordigitalcalibrationin0.05ppmresolution
To digitally calibrate the free running clock synthesized from the internal clock, this register is written with a value cor-
responding to the known frequency offset of the oscillator from the nominal center frequency.
Fr_Pulse_Width, 0x10 (R/W)
Bit 7 ~ Bit4
Bit 3 ~ Bit 0
Reserved
PulsewidthforM/Sclockoutput,
1-15multiplesoftheSync_Clkclockperiod.
BITS 4 and 5 of the
Ctl_Mode register determine if the M/S 8 kHz output is 50% duty cycle or pulsed (high going) out-
puts. When they are pulsed, the
Fr_Pulse_Width register determines the width. Width is the register value multiple of the
Sync_Clk clock period. Valid values are 1 - 15.
Reset default is 0001. Writing to 0000 maps to 0001.
DPLL_Status, 0x11 (R)
Bit 7 ~Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
HoldOver
Locked
LossofLock
LossofSignal
Build
Available
1:Locked
1:LossofLock
1:Noactivity
Complete
1:Avail.
0:Notlocked
0:Nolossoflock
onactive
1:Complete
0:Notavail.
reference
0:Incomplete
0:Activeref-
erencesignal
present
Bit 0 indicates the presence of a signal on the selected reference.
Bit 1 indicates a loss of lock (LOL). Loss of lock will be asserted if lock is not achieved within the specified time for the
stratum level of operation, or lock is lost after being established previously. LOL will not be asserted for automatic refer-
ence switches.
Bit 2 indicates successful phase lock. It will typically be set in <100 seconds for stratum 3 with a good reference. It will
indicate “not locked” if lock is lost.
Bit 3 indicates if a Hold Over history is available.
Bit 4 indicates when a new Hold Over history has been sucessfully built and transferred to the active Hold Over history.
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