參數(shù)資料
型號(hào)： SM3-19.44M
廠商： Connor-Winfield
文件頁(yè)數(shù)： 36/36頁(yè)
文件大?。?/td> 0K
描述： IC MOD TIMING 19.440MHZ STATUM 3
標(biāo)準(zhǔn)包裝： 1
系列： SM3
類(lèi)型： 定時(shí)模塊，系統(tǒng)時(shí)鐘
PLL： 是
主要目的： 以太網(wǎng)，ADM，DSLAM，SONET/SDH，Stratum，TDM
輸入： LVCMOS
輸出： LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 4:3
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 19.44MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 通孔
封裝/外殼： 32-DIP 模塊
包裝： 管件
其它名稱(chēng)： CW642
SM3 19.44M
SM319.44M
SM3 Data Sheet #:
TM052
Page 9 of 36 Rev: 06 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Reference Input Quality Monitoring
Each reference input is monitored for signal presence and frequency offset. Signal presence for the
Ref1-4 inputs is indicated in
the
Ref_Activity register and signal presence for the M/S REF is indicated in bit 0 of the M/S REF_Activity register. The frequency
offset between the
Ref1-4 inputs and the calibrated local oscillator is available in the Ref_Frq_Offset registers (4). Register Ref_
Pullin_Sts indicates, for each of the Ref1-4 inputs, if the reference is within the maximum pull-in range. The maximum pull-in range
is indicated in register
Max_Pullin_Range, and may be set in 0.1ppm increments. Typically, it would be set according to the values
specified by the standards (GR-1244) appropriate for the particular stratum of operation.
The
Ref_Qualified register contains the “anded” condition of the Ref_Activity and Ref_Pullin_Sts registers for each of the Ref1-4
inputs, qualified for 10 seconds. When a reference signal has been present for > 10 seconds and is within the pull-in range, it’s bit is
set.
The
Ref_Available register contains the “anded” condition of the Ref_Qualified register and the Ref_Mask register, and therefore
represents the availability of a reference for selection when automatic reference and operational mode selection is enabled.
Reference Input Selection, Frequencies, and Mode Selection
One of four reference input signals (
Ref 1-4) are selected for synchronization in Master mode (as below in the Op_Mode register
description. 0x05).
Ref1-4 may each be 8 kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz
or 77.76 MHz.
Reference frequencies are auto-detected (frequency determined by the chip) and the detected frequency can be read from the
Ref_Frq_Priority registers (See Register Descriptions and Operation section).
The M/S REF input for slave operation is frequency auto-detected and may be 8kHz, 1.544MHz, 2.048MHz, 12.96MHz, 19.44MHz,
25.92MHz, 38.88MHz, 51.84MHz or 77.76MHz. Signal presence and frequency for the M/S REF input is indicated in bits 0-3 of the
M/S REF_Activity register.
Active reference and operational mode selection may be manual or automatic, as determined by bit 1 in the Ctl_Mode register. In
manual mode, register writes to Op_Mode select the reference and mode. The reset default is manual mode.
In automatic mode, the reference is selected according to the priorities written to the four
Ref_Frq_Priority registers. Individual
references may be masked for use/non-use according to the
Ref_Mask register. A reference may only be selected if it is “available”
- that is, it is qualified, as indicated in the
Ref_Qualified register, and is not masked (See Reference Input Quality Monitoring and
Register Descriptions and Operation sections).
Furthermore, Bit 3 of each
Ref_Frq_Priority register will determine if that reference is revertive or non-revertive. When a reference
fails, the next highest priority “available” (signal present, non-masked, and acceptable frequency offset) reference will be selected.
When a reference returns, it will be switched to only if it is of higher priority and the current active reference is marked “Revertive”.
Additionally, the reversion is delayed according to the value written to the
Ref_Rev_Delay register (From 0 to 255 minutes).
Detailed Description continued
Serial Interface Timing
Table 4
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
t
CS
SPI_EnablelowtoSPI_CLKlow
15
-
ns
t
CH
SPI_CLKhightime
25
-
ns
t
CL
SPI_CLKlowtime
25
-
ns
t
RWs
Read/Writesetuptime
15
-
ns
t
RWh
Read/Writeholdtime
15
-
ns
t
DRDY
Dataready
-
25
ns
t
HLD
DataHold
15
-
ns
t
CSTRI
ChipSelecttodatatri-state
5
-
ns
t
CSMIN
Minimumdelaybetweensuccessiveaccesses 300
-
ns
Note:TheSPIportshouldnotbeaccesseduntil1200msafterresethastransitionedfromlowtoahighstate.
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