參數(shù)資料
型號: SM3-19.44M
廠商: Connor-Winfield
文件頁數(shù): 5/36頁
文件大?。?/td> 0K
描述: IC MOD TIMING 19.440MHZ STATUM 3
標(biāo)準(zhǔn)包裝: 1
系列: SM3
類型: 定時模塊,系統(tǒng)時鐘
PLL:
主要目的: 以太網(wǎng),ADM,DSLAM,SONET/SDH,Stratum,TDM
輸入: LVCMOS
輸出: LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 4:3
差分 - 輸入:輸出: 無/無
頻率 - 最大: 19.44MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 32-DIP 模塊
包裝: 管件
其它名稱: CW642
SM3 19.44M
SM319.44M
SM3 Data Sheet #:
TM052
Page 13 of 36 Rev: 06 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Register Descriptions and Operation continued
Op_Mode, 0x05 (R/W)
Bit 7 ~ Bit 5
Bit 4
Bit 3 ~ Bit 0
Reserved
MasterorSlaveMode
FreeRun,Locked,orHoldOver:
1:Master
0000:FreeRunmode
0:Slave
0001:LockedonRef1
(ReadOnly)
0010:LockedonRef2
0011:LockedonRef3
0100:LockedonRef4
0101-1000:NotUsed
1001-1111:HoldOver
Max_Pullin_Range, 0x06 (R/W)
Bit 7 ~ Bit 0
Maximumpull-inrangein0.1ppmunit
This register should be set according to the values specified by the standards (GR-1244) appropriate for the particular
stratum of operation. The power-up default value is 10 ppm. (= 4.6ppm aging + 4.6 ppm pullin + margin).
M/S_Activity, 0x07 (R)
Bit 7 ~ Bit 4
Bit 3 ~ Bit 0
Reserved
Crossreferenceactivity
0000:Nosignal
0001:8kHz
0010:1.544MHz
0011:2.048MHz
0100:12.96MHz
0101:19.44MHz
0110:25.92MHz
0111:38.88MHz
1000:51.84MHz
1001:77.76MHz
1010-1111:Reserved
Indicates signal presence and auto-detected frequency for the
M/S REF input.
Ref_Activity, 0x08 (R)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ref4activity
ref3activity
ref2activity
ref1activity
x:Don’t
1:on
Care
0:off
Each bit indicates the presence of a signal for that reference. Reference bits 4-7 are not used but may be 1 or 0.
When the device is in slave mode, it will lock to the
M/S REF, independent of the values written to BITS 3 - 0 of the
Op_mode register. The operational mode and reference selection written to Bits 3 - 0 while in slave mode will, however,
take effect when the device is made the master.
When bit 1 of the
Ctl_Mode register is reset (automatic reference and mode selection) and the device is in master
mode, BITS 3 - 0 of the
Op_Mode register become read-only.
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