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參數(shù)資料
| 型號(hào)： | SM3-19.44M |
| 廠商： | Connor-Winfield |
| 文件頁(yè)數(shù)： | 3/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MOD TIMING 19.440MHZ STATUM 3 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SM3 |
| 類型： | 定時(shí)模塊，系統(tǒng)時(shí)鐘 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，ADM，DSLAM，SONET/SDH，Stratum，TDM |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 19.44MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-DIP 模塊 |
| 包裝： | 管件 |
| 其它名稱： | CW642 SM3 19.44M SM319.44M |
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SM3 Data Sheet #:
TM052
Page 11 of 36 Rev: 06 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Detailed Description continued
Output Signals and Frequency
Output 1 is the primary output, and in locked mode is synchronized to the selected reference. Output 1 must be specified at the
time of ordering as any one of the following frequencies : 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz or 77.76 MHz.
M/S Output is an 8 kHz output available as a frame reference or synchronization signal for cross-coupled pairs of SM3 devices
operated in master/slave mode. In master mode, M/S Output is synchronized to the selected reference. In slave mode, M/S Output
is in phase with the
M/S REF offset by the value written to the Phase_offset register (+31.75 to -32nS, with .25nS resolution). M/S
Output may be a 50% duty cycle signal, or variable high-going pulse width, as determined by the
Ctl_Mode and Fr_Pulse_Width
registers. In variable pulse width mode, the width may be from 1 to 15 multiples of the Output 1 cycle time. See Register Descriptions
and Operation section.
BITS_Clk is the BITS clock output at either 1.544 MHz or 2.048 MHz. It is selected by the T1/E1 input and its state may be read in
bit 3 of the
Ctl_Mode register. When T1/E1 = 1, the BITS frequency is 1.544 MHz, and when T1/E1 = 0, the BITS frequency is 2.048
MHz. This output clock is digitally synthesized from Output1 directly and will be synchronized to M/S Output.
Interrupts
The SM3 module supports eight different interrupts and appears in
INTR_EVENT (0x12) register. Each interrupt can be individually
enabled or disabled via the
INTR_ENABLE (0x13) register. Each bit enables or disables the corresponding interrupt from asserting
the
SPI_INT pin. Interrupt events still appear in the INTR_EVENT (0x12) register independent of their enable state. All interrupts are
cleared once
INTR_EVENT (0x12) register is read. The interrupts are:
Any reference changing from available to not available
Any reference changing from not available to available
M/S REF changing from activity to no activity
M/S REF changing from no activity to activity
DPLL Mode status change
Reference switch in automatic reference selection mode
Loss of Signal
Loss of Lock
Interrupts and Reference Change in Autonomous Mode
Interrupts can be used to determine the cause of a reference change in autonomous mode. Let us assume that the module is
currently locked to
REF1. The module switches to REF2 and SPI_INT pin is asserted. The user reads the INTR_EVENT (0x12)
register.
If the module is operating in autonomous revertive mode, the cause can be determined from bits 1, 4,5, 6 and 7. Bit 5 is set to
indicate Active reference change. If Bit 6 is set then the cause of the reference change is Loss of Active Reference. If Bit 7 is set
then the cause of the reference change is a Loss of Lock alarm on the active reference. If Bit 1 is set then the cause of the reference
change is the availability of a higher priority reference.
Note: The DPLL Mode Status Change bit (Bit 4) is also set to indicate a change in DPLL_STATUS (0x11) register, during an
interrupt caused by a reference change. The data in
DPLL_STATUS (0x11) register however is not useful in determining the cause of
a reference change. This is because bits 0-2 of this register always reflects the status of the current active reference and hence cannot
be used to determine the status of the last active reference.
Interrupts in Manual Mode
In manual operating mode, when the active reference fails due to a Loss of Signal or Loss of Lock alarm, an interrupt is generated.
For example, in case of a Loss of Signal, bits4 and 6 of
INTR_EVENT (0x12) register would be set to indicate Loss of Signal and
DPLL Mode Status Change. The user may choose to read the
DPLL_STATUS (0x11) register, though in manual mode bit6 of INTR_
EVENT (0x12) register is a mirror of bit0 of DPLL_STATUS (0x11) register. This holds true for a Loss of Lock alarm, where bit7 of
INTR_EVENT (0x12) register is a mirror of bit1 of DPLL_STATUS (0x11) register.
Internal Clock Calibration
The internal clock may be calibrated by writing a frequency offset v.s. nominal frequency into the Calibration register. This
calibration is used by the synchronization software to create a frequency corrected from the actual internal clock output by the value
written to the Calibration register. See register descriptions.
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