參數(shù)資料
型號： SII3114_07
廠商： Silicon Image, Inc.
英文描述： PCI to Serial ATA Controller
中文描述： PCI到Serial ATA控制器
文件頁數(shù)： 95/127頁
文件大小： 598K
代理商： SII3114_07
SiI
3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Table 31 shows the default configurations of all Serial ATA FIS types.
2007 Silicon Image, Inc.
87
SiI
-DS-0103-D
Table 31. Default FIS Configurations
Configuration Bits
Register Bits
FIS27cfg[1:0]
FIS34cfg[1:0]
FIS39cfg[1:0]
FIS41cfg[1:0]
FIS46cfg[1:0]
FIS58cfg[1:0]
FIS
Code
FIS Name
Default Value
01b
00b
00b
01b
00b
00b
Comments
27h
34h
39h
41h
46h
58h
Register (Host to Device)
Register (Device to Host)
DMA Activate
DMA Setup
Data
BIST Activate
Default to reject FIS without interlock.
Default to accept FIS without interlock.
Default to accept FIS without interlock.
Default to reject.
Default to accept FIS without interlock.
Default to accept for far-end retimed loopback,
reject for any other.
Default to accept FIS without interlock.
Default to accept FIS without interlock.
Default to reject FIS without interlock.
Default to reject FIS without interlock.
Default to reject FIS without interlock.
Default to reject FIS without interlock.
Default to reject FIS without interlock.
Default to reject FIS without interlock.
Default to reject FIS without interlock.
5Fh
A1h
A6h
B8h
BFh
C7h
D4h
D9h
Others reserved
PIO Setup
Set Device Bits
reserved
reserved
reserved
reserved
reserved
reserved
FIS5Fcfg[1:0]
FISa1cfg[1:0]
FISa6cfg[1:0]
FISb8cfg[1:0]
FISbFcfg[1:0]
FISc7cfg[1:0]
FISd4cfg[1:0]
FISd9cfg[1:0]
FISocfg[1:0]
00b
00b
01b
01b
01b
01b
01b
01b
01b
RxFIS[0-6]- First seven dwords received from device. RxFIS[0] is the first dword that contains the FIS header.
RxFIS[6] is the last of the seven dwords received. It is enough to support DMA Setup FIS.
Note that:
FIS data can also be read out directly from RxFIS (first seven dwords).
All data to be transferred must be sent within one UDMA burst. Burst termination will not be allowed and
may produce unpredictable result.
There is no limit on received frame size.
In a Data FIS, the receive FIFO will automatically advance one dword to skip the header. Upon an
interlocked FIS, the FIFO read pointer will rewind to the beginning so that the first dword read is the
header.
The following summarizes the behavior:
On power up, the default configurations are as follows:
All defined FISes, except BIST Activate and DMA Setup, default to be supported (FISxxcfg[1:0] = '00').
BIST Activate is default to be accepted ONLY for Far-end Retimed Loopback and to be rejected for any
other BIST types.
DMA Setup defaults to be rejected.
All undefined FISes default to be rejected (FISxxcfg[1:0] = '01').
Sequences:
Upon reception of an unsupported FIS (FISxxcfg[1:0] = '01'), the Link/Transport Logic responds with
R_ERR to the downstream device. The host will not be notified.
Upon reception of a supported FIS (FISxxcfg[1:0] = '00'), the Link/Transport Logic responds with
R_OK at WTRM (if no error is detected) or R_ERR (if an error is detected) to the downstream device.
The host will be notified only as required by the protocol.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SII3114CT176 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI to Serial ATA Controller
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SII3124A 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller
SII3124ACBHU 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller
SII3132 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller
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