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| 型號(hào)： | SII3114_07 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI to Serial ATA Controller |
| 中文描述： | PCI到Serial ATA控制器 |
| 文件頁(yè)數(shù)： | 61/127頁(yè) |
| 文件大?。?/td> | 598K |
| 代理商： | SII3114_07 |
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SiI
3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2007 Silicon Image, Inc.
53
SiI
-DS-0103-D
PCI Bus Master – Channel
X
Address Offset: 00
H
/ 08
H
/ 200
H
/ 208
H
Access Type: Read/Write
Reset Value: 0x0000_XX00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
P
P
P
R
C
X
P
P
W
C
X
D
Software
Reserved
P
R
I
P
This register defines the PCI bus master register for Channel
X
in the
SiI
3114. The register bits are defined below.
Bit [31:24]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [23]
: PBM Simplex (R) – PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to
indicate that all channels can operate as PCI bus master at any time.
Bit [22]
: PBM DMA Cap 1 (R/W) – PCI Bus Master DMA Capable – Device 1. This bit field has no effect.
The device is always capable of DMA as a PCI bus master.
Bit [21]
: PBM DMA Cap 0 (R/W) – PCI Bus Master DMA Capable – Device 0. This bit field has no effect.
The device is always capable of DMA as a PCI bus master.
Bit [20:19]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [18]
: Channel
X
DMA Comp (R/W1C) – Channel
X
DMA Completion Interrupt. During write DMA
operation, this bit set indicates that the Channel
X
interrupt has been asserted and all data has been
written to system memory. During Read DMA, This bit set indicates that the Channel
X
interrupt has been
asserted.
This bit must be cleared (Write 1 to Clear) by software when set during DMA operation (PBM Enable, bit 0
is set).
Bit [17]
: PBM Error (R/W1C) – PCI Bus Master Error – Channel
X
. This bit set indicates that a PCI bus
error occurred while the
SiI
3114 was bus master. Additional information is available in the PCI Status
register in PCI Configuration space.
Bit [16]
: PBM Active (R) – PCI Bus Master Active – Channel
X
. This bit set indicates that the
SiI
3114 is
currently active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data
transfers have completed or PBM Enable bit is not set.
Bit[15]
: Watchdog Timer Status (R) – This bit is an ORed result of bit 12 in the four Channel Task File
Timing + Configuration + Status registers. When set indicates that one or more of the four Channel
Watchdog timers has expired. This bit appears only in the Channel 0 (offset 00
H
) and Channel 2 (offset
200
H
) registers; this bit is reserved in the Channel 1 (offset 08
H
) and Channel 3 (offset 208
H
) registers.
Bit[14]
: Channel
X+1
Interrupt Status (R) – This bit is a copy of the Channel
X
DMA Completion Interrupt
(bit 18) in the PCI Bus Master (this) register for Channel
X+1
. This bit appears only in the Channel 0 (offset
00
H
) and Channel 2 (offset 200
H
) registers; this bit is reserved in the Channel 1 (offset 08
H
) and Channel 3
(offset 208
H
) registers.
Bit [13:08]
: Software Data (R/W) – System Software Data Storage. This bit field is used for read/write data
storage by the system. The properties of this bit field are detailed below. This bit field appears only in the
Channel 0 (offset 00
H
) and Channel 2 (offset 200
H
) registers; this bit field is reserved in the Channel 1
(offset 08
H
) and Channel 3 (offset 208
H
) registers.
Table 23. Software Data Byte, Base Address 5, Offset 00
H
Bit Location
[13:12]
[11:10]
[09:08]
Default
XX
B
00
B
XX
B
Description
Not cleared by any reset
Cleared by PCI reset
Cleared only by a D0-D3 power state change
Bit [07:04]
: Reserved (R). This bit field is reserved and returns zeros on a read.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SiI3114CT176 | PCI to Serial ATA Controller |
| SiI3114CTU | PCI to Serial ATA Controller |
| SII3124A | PCI-X to Serial ATA Controller |
| SiI3124ACBHU | PCI-X to Serial ATA Controller |
| SII3132 | PCI Express to 2-Port Serial ATA II Host Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3114CT176 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI to Serial ATA Controller |
| SII3114CTU | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 176-Pin TQFP 制造商:SILICON 功能描述: |
| SII3124A | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3124ACBHU | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3132 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
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