參數(shù)資料
型號: SII3114_07
廠商: Silicon Image, Inc.
英文描述: PCI to Serial ATA Controller
中文描述: PCI到Serial ATA控制器
文件頁數(shù): 93/127頁
文件大小: 598K
代理商: SII3114_07
SiI
3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
FIS Support
FIS Summary
2007 Silicon Image, Inc.
85
SiI
-DS-0103-D
Table 29 summarizes the implementation of FIS Support. Note that 14 FIS codes meet the criteria of FIS code
selection in Serial ATA, and 8 out of the 14 are already defined.
Table 29. FIS Summary
FIS
Code
27h
FIS Name
Host to
Device
Device
to Host
-
Comment
Register (Host to Device)
Support Expanded Registers
HOB not sent to device (device dongle ignores HOB received)
Can be individually controlled via PCI registers - default to
reject
Support Expanded Registers
Host to Device transmission is possible as Transparent.
Can be individually controlled via PCI registers - default to
accept
Supported per Serial ATA specification.
Host to Device transmission is possible as Transparent.
Can be individually controlled via PCI registers - default to
accept
On reception, the first 7 dwords of any FIS can be read directly
by the PCI.
Transmission: As transparent FIS
Can be individually controlled via PCI registers - default to
reject
Supported per Serial ATA specification.
Can be individually controlled via PCI registers - default to
accept
Support for reception of Far-End Retimed Loopback. No
transmission supported.
Can be individually controlled via PCI registers - default to
accept for Far-End Retimed Loopback; default to reject for all
other BIST types
Supported per Serial ATA specification.
Host to Device transmission is possible as Transparent.
Can be individually controlled via PCI registers - default to
accept
Supported per Serial ATA specification
Host to Device transmission is possible as Transparent
Can be individually controlled via PCI registers - default to
accept
Supported as one group of unrecognized FIS, together with
other unsupported FISes, such as "Others" below, and FIS
Code 27h in the reception direction.
Can be individually controlled via PCI registers - default to
reject
34h
Register (Device to Host)
-
39h
DMA Activate
-
41h
DMA Setup
46h
Data
58h
BIST Activate
5Fh
PIO Setup
-
A1h
Set Device Bits
-
A6h
B8h
BFh
C7h
D4h
D9h
Others Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Supported as one group of unrecognized FIS, together with
other unsupported FISes (FIS Code 27h, A6h, B8h, BFh, C7h,
D4h, D9h) in the reception direction.
All "Others" are controlled as a group via PCI registers -
default to reject
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