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參數(shù)資料
| 型號(hào)： | SIHF830-E3 |
| 廠商： | VISHAY SILICONIX |
| 元件分類： | JFETs |
| 英文描述： | 4.5 A, 500 V, 1.5 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB |
| 封裝： | ROHS COMPLIANT, TO-220, 3 PIN |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 201K |
| 代理商： | SIHF830-E3 |
Document Number: 91063
S11-0506-Rev. B, 21-Mar-11
www.vishay.com
7
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc91000
IRF830, SiHF830
Vishay Siliconix
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see
www.vishay.com/ppg91063
.
P.W.
Period
dI/dt
Diode recovery
dV/dt
Ripple
≤
5 %
Body diode forward drop
Re-applied
voltage
Rever
s
e
recovery
current
Body diode forward
current
V
GS
= 10 V
a
I
S
D
Driver gate drive
D.U.T. l
S
D
waveform
D.U.T. V
D
S
waveform
Inductor current
D =
P.W.
Period
+
-
+
+
+
-
-
-
Peak Dio
d
e Recovery
d
V/
d
t Test Circuit
V
DD
dV/dt controlled by R
Driver
s
ame type a
s
D.U.T.
I
controlled by duty factor “D”
D.U.T. - device under te
s
t
D.U.T.
Circuit layout con
s
ideration
s
Low
s
tray inductance
G
round plane
Low leakage inductance
current tran
s
former
R
g
Note
a. V
GS
= 5 V for logic level device
s
V
DD
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