tRF CLOAD = 20 pf See Figure 2 —25 — ns LOSn Trigg" />
參數(shù)資料
型號: SI5315-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 54/54頁
文件大?。?/td> 0K
描述: BOARD EVAL SI5315 8KHZ-644.53MHZ
應用說明: SI5315/17 Crystal Selection AppNote
標準包裝: 1
主要目的: 計時,時鐘乘法器
嵌入式:
已用 IC / 零件: SI5315
主要屬性: 2 輸入,2 輸出
次要屬性: CML,CMOS,LVDS,LVPECL
已供物品: 板,CD,文檔
Si5315
Rev. 1.0
9
LVCMOS Output Pins
Rise/Fall Times
tRF
CLOAD = 20 pf
—25
ns
LOSn Trigger Window
LOSTRIG
From last CKINn
to
internal detection of LOSn
——
750
s
Time to Clear LOL after LOS
Cleared
tCLRLOL
LOS to LOL
Assume Fold=Fnew,
Stable XA-XB reference
—10
ms
PLL Performance
Output Clock Skew
tSKEW
of CKOUTn to CKOUTn
100
ps
Phase Change Due to
Temperature Variation
tTEMP
Maximum phase change from
–40 to +85 °C
300
500
ps
Lock Time
tLOCKHW RST with valid CKIN to LOL;
BW = 100 Hz
1200
ms
Closed Loop Jitter Peaking
JPK
—0.05
0.1
dB
Jitter Tolerance
JTOL
ns pk-
pk
Minimum Reset Pulse Width
tRSTMIN
1—
s
Output Clock Initial Phase Step
tP_STEP
During clock switch CKIN > 19.44
MHz
100
200
ps
Holdover Frequency Historical
Averaging Time
tHISTAVG
—6.7
sec
Holdover Frequency Historical
Delay Time
tHISTDEL
—26.2
ms
Spurious Noise
SPSPUR
Max spur @ n x f3
(n > 1, n x f3 < 100 MHz)
—–75
dBc
Table 3. AC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Notes:
1. Assumes N3 does not equal 1. IF N3 = 1, CKNDC = 50 s.
2. Refers to Si5315A speed grade.
3. Refers to Si5315B speed grade.
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