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參數(shù)資料
| 型號： | SI5315-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 40/54頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL SI5315 8KHZ-644.53MHZ |
| 應用說明： | SI5315/17 Crystal Selection AppNote |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘乘法器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | SI5315 |
| 主要屬性： | 2 輸入，2 輸出 |
| 次要屬性： | CML，CMOS，LVDS，LVPECL |
| 已供物品： | 板，CD，文檔 |
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Si5315
Rev. 1.0
45
14
DBL2_BY
I
3-Level
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled
M = CKOUT2 disabled
H = Bypass mode with CKOUT2 enabled. Bypass mode is
not supported with CMOS clock outputs (SFOUT = LH).
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
16
17
CKIN1+
CKIN1–
IMulti
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
18
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indica-
tor.
0 = PLL locked
1 = PLL unlocked
21
CS_CA
I/O
LVCMOS
Input Clock Select/Active Clock Indicator.
Input:
If manual clock selection mode is chosen
(AUTOSEL = L), this pin functions as the manual
input clock selector. This input is internally deglitched
to prevent inadvertent clock switching during
changes in the CS input state.
0 = Select CKIN1
1 = Select CKIN2
If configured as input, must be set high or low.
Output: If automatic clock selection mode is chosen
(AUTOSEL = M or H), this pin indicates which of the
two input clocks is currently the active clock. If
alarms exist on both CKIN1 and CKIN2, indicating
that the holdover state has been entered, CA will
indicate the last active clock that was used before
entering the hold state.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
23
22
BWSEL1
BWSEL0
I3-Level
Loop Bandwidth Select.
Three level inputs that select the DSPLL closed loop band-
width. See Table 9 on page 20 for available settings.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Table 19. Si5315 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
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| SI5315-H | 制造商:KODENSHI 制造商全稱:KODENSHI KOREA CORP. 功能描述:Colorless transparency lens type |
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| SI5315-H_1 | 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED |
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