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參數(shù)資料
| 型號(hào)： | SI5315-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 41/54頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL SI5315 8KHZ-644.53MHZ |
| 應(yīng)用說(shuō)明： | SI5315/17 Crystal Selection AppNote |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘乘法器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | SI5315 |
| 主要屬性： | 2 輸入，2 輸出 |
| 次要屬性： | CML，CMOS，LVDS，LVPECL |
| 已供物品： | 板，CD，文檔 |
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Si5315
46
Rev. 1.0
27
26
25
24
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
I3-Level
Frequency Select.
Three level inputs that select the input clock and clock multi-
plication ratio, depending on the FRQTBL setting.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
29
28
CKOUT1–
CKOUT1+
OMulti
Clock Output 1.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML com-
patible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
33
30
SFOUT0
SFOUT1
I3-Level
Signal Format Select.
Three level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
34
35
CKOUT2–
CKOUT2+
OMulti
Clock Output 2.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML com-
patible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
36
NC
—
No Connect.
Leave floating. Make no external connections to this pin for
normal operation.
GND
PAD
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Table 19. Si5315 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
SFOUT[1:0]
Signal Format
HH
Reserved
HM
LVDS
HL
CML
MH
LVPECL
MM
Reserved
ML
LVDS—Low Swing
LH
CMOS
LM
Disable
LL
Reserved
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