參數(shù)資料
型號: SI5315-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 37/54頁
文件大?。?/td> 0K
描述: BOARD EVAL SI5315 8KHZ-644.53MHZ
應(yīng)用說明: SI5315/17 Crystal Selection AppNote
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘乘法器
嵌入式:
已用 IC / 零件: SI5315
主要屬性: 2 輸入,2 輸出
次要屬性: CML,CMOS,LVDS,LVPECL
已供物品: 板,CD,文檔
Si5315
42
Rev. 1.0
9. Typical Phase Noise Plots
The following is a typical phase noise plot. The clock input source was a Rohde and Schwarz model SML03 RF
Generator. The spectrum analyzer was either an Agilent model E5052B, model E4400A or model JS-500. The
Si5315 operates at 3.3 V with an ac coupled differential PECL output and an ac coupled differential sine wave input
from the RF generator at 0 dBm. Note that, as with any PLL, the output jitter that is below the loop BW is caused by
the jitter at the input clock, not the Si5315. Except as noted, loop BWs of 60 to 240 Hz were in use.
9.1. 10G LAN SyncE Example
Frequency Plan
Fin=19.44 MHz
Fout=156.25 MHz
BW=167 Hz
Fin=19.44 MHz
Fout=125 MHz
BW=111 Hz
Fin=25 MHz
Fout=156.25 MHz
BW=111 Hz
Fin=25 MHz
Fout=125 MHz
BW=111 Hz
Jitter Integration Filter Band
RMS Jitter (fs)
IEEE802.3 (1.875 to 20 MHz)
232
240
251
240
SONET OC-192 (20 kHz to 80 MHz)
483
575
525
550
SONET OC-192 (4 to 80 MHz)
302
303
300
294
SONET OC-192 (50 kHz to 80 MHz)
467
564
510
537
SONET OC-48 (12 kHz to 20 MHz)
470
565
517
541
SONET OC-3 (12 kHz to 5 MHz)
422
524
471
503
BroadBand (800 Hz to 80 MHz)
511
584
533
557
‐180
‐160
‐140
‐120
‐100
‐80
‐60
‐40
‐20
0
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Si5315TypicalPhaseNoise
Fin=19.44MHz;
Fout=125MHz;
BW=111Hz
Fin=19.44MHz
Fout=156.25MHz
BW=167Hz
Fin=25MHz
Fout=125MHz
BW=111Hz
Fin=25MHz
Fout=156.25MHz
BW=111Hz
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