(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V " />
參數(shù)資料
型號: SI5315-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 5/54頁
文件大小: 0K
描述: BOARD EVAL SI5315 8KHZ-644.53MHZ
應(yīng)用說明: SI5315/17 Crystal Selection AppNote
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘乘法器
嵌入式:
已用 IC / 零件: SI5315
主要屬性: 2 輸入,2 輸出
次要屬性: CML,CMOS,LVDS,LVPECL
已供物品: 板,CD,文檔
Si5315
Rev. 1.0
13
Table 7. Thermal Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Thermal Resistance
Junction to Ambient
JA
Still Air
32
C/W
Thermal Resistance
Junction to Case
JC
Still Air
14
C/W
Table 8. Absolute Maximum Limits
Parameter
Symbol
Value
Unit
DC Supply Voltage
VDD
–0.5 to 3.8
V
LVCMOS Input Voltage
VDIG
–0.3 to (VDD + 0.3)
V
CKINn Voltage Level Limits
CKNVIN
0 to VDD
V
XA/XB Voltage Level Limits
XAVIN
0 to 1.2
V
Operating Junction Temperature
TJCT
–55 to 150
C
Storage Temperature Range
TSTG
–55 to 150
C
ESD HBM Tolerance (100 pF, 1.5 k
); All pins except
CKIN+/CKIN–
2kV
ESD MM Tolerance; All pins except CKIN+/CKIN–
150
V
ESD HBM Tolerance (100 pF, 1.5 k
); CKIN+/CKIN–
750
V
ESD MM Tolerance; CKIN+/CKIN–
100
V
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
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