(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, " />
參數(shù)資料
型號(hào): SI5315-EVB
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 53/54頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL SI5315 8KHZ-644.53MHZ
應(yīng)用說(shuō)明: SI5315/17 Crystal Selection AppNote
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘乘法器
嵌入式:
已用 IC / 零件: SI5315
主要屬性: 2 輸入,2 輸出
次要屬性: CML,CMOS,LVDS,LVPECL
已供物品: 板,CD,文檔
Si5315
8
Rev. 1.0
Table 3. AC Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Input Frequency
CKNF
0.008
644.53
MHz
CKINn Input Pins
Input Duty Cycle (Minimum
Pulse Width)
CKNDC
Whichever is smaller1
40
60
%
2—
ns
Input Capacitance
CKNCIN
——
3
pF
Input Rise/Fall Time
CKNTRF
20–80%
——
11
ns
CKOUTn Output Pins
Output Frequency (Output not
configured for CMOS or disable)
CKOF
Note 2
0.008
644.53
MHz
Note 3
0.008
125
MHz
Maximum Output Frequency in
CMOS Format
CKOFMC
161.13
MHz
Output Rise/Fall (20–80%) at
644.5313 MHz
CKOTRF Output not configured for CMOS
or disabled, see Figure 2
230
350
ps
Single Ended Output Rise/Fall
(20–80%)
CKOTRF
CMOS Output
VDD = 1.62
Cload = 5 pF
——
8
ns
CMOS Output
VDD = 2.97
Cload = 5 pF
——
2
ns
Output Duty Cycle Differential
Uncertainty
CKODC
100
Load
Line to Line
Measured at 50% Point
(not for CMOS)
——
±40
ps
LVCMOS Pins
Input Capacitance
Cin
——
3
pF
Notes:
1. Assumes N3 does not equal 1. IF N3 = 1, CKNDC = 50 s.
2. Refers to Si5315A speed grade.
3. Refers to Si5315B speed grade.
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