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參數(shù)資料
| 型號： | SI3062-F-FS |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 8/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAA ENH FCC LINE-SIDE 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 功能： | 直接存取裝置（DAA） |
| 電路數(shù)： | 1 |
| 電流 - 電源： | 9mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 管件 |
| 包括： | 結(jié)帳音調(diào)檢測，線路電壓監(jiān)視器，回路電流監(jiān)視器，過載檢測，振鈴檢測器 |
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Si306x
16
Rev. 0.9
6.2. Power Supplies
The Si306x line-side device derives its power from two
sources: The system-side module and the telephone
line. The integrated system-side module supplies power
over the patented capacitive isolation link between the
two
devices,
allowing
the
line-side
device
to
communicate with the system-side module while on-
hook and perform other on-hook functions such as line
voltage monitoring. When off-hook, the line-side device
also derives power from the line current supplied from
the telephone line. This feature is exclusive to DAAs
from Silicon Laboratories and allows the most cost
effective
implementation
for
a
DAA
while
still
maintaining robust performance over all line conditions.
6.3. Initialization
When the integrated system-side module is powered
up, assert the RESET pin. When the RESET pin is
deasserted, the registers have default values. This reset
condition guarantees the line-side device is powered
down without the possibility of loading the line (i.e., off-
hook). An example initialization procedure is outlined in
the following list:
1. Program the desired sample rate with the Sample
Rate Control Register (Register 7).
2. Wait until the line-side PLL is locked. This time is
normally between 100 s and 1 ms from the
application of MCLK.
3. Write a 00H into the DAA Control Register
(Register 6) to power up the line-side device.
4. Set the required line interface parameters MINI[1:0],
ILIM, DCR, ACT and ACT2, OHS, RT, RZ, ATX[2:0]
and ARX[2:0] as defined by “Country Specific
Register Settings” shown in Table 7.
When this procedure is complete, the Si306x is ready
for ring detection and off-hook.
6.4. Isolation Barrier
The Si306x achieves an isolation barrier through low-
cost, high-voltage capacitors in conjunction with Silicon
Laboratories’ proprietary signal processing techniques.
These techniques eliminate signal degradation from
capacitor mismatches, common mode interference, or
noise coupling. As shown in "3. Typical Application
Schematic" on page 9, the C1, C2, C8, and C9
capacitors isolate the integrated system-side module
from the line-side device. Transmit, receive, control, ring
detect, and caller ID data are passed across this barrier.
Y2 class capacitors can be used to achieve surge
performance of 5 kV or greater.
The proprietary capacitive communications link is
disabled by default. To enable it, the PDL bit
(Register 6, bit 4) must be cleared. No communication
between the system-side and line-side can occur until
this bit is cleared.
6.5. Power Management
The DAA supports four basic power management
operation modes. The modes are normal operation,
reset operation, sleep mode, and full powerdown mode.
PDN and PDL bits (Register 6) control the power
management modes.
On powerup, or following a reset, the DAA is in reset
operation. The PDL bit is set, and the PDN bit is
cleared. The system-side module is operational, except
for the communications link. No communication
between the system-side module and the Si306x line-
side device can occur during reset operation. Bits
associated with the line-side device are not valid in this
mode.
The most common mode of operation is the normal
operation. In this mode, the PDL and PDN bits are
cleared.
The
DAA
is
operational
and
the
communications link is passing information between the
Si306x and the line-side device.
The Si306x supports a low-power sleep mode that
supports the wake-up-on-ring feature of many modems.
The clock generator registers 7, 8, and 9 must be
programmed with valid, non-zero values before
enabling sleep mode. The PDN bit must be set and the
PDL bit cleared. When the Si306x is in sleep mode, the
host processor clock signal must remain active to
support ring validation and wake-on-ring features. In low
power sleep mode, the system-side module is non-
functional except for the communications link and the
RGDT signal. To take the Si306x out of sleep mode, the
system-side module should be reset.
In summary, the powerdown/up sequence for sleep
mode is as follows:
1. Ensure that Registers 7, 8, and 9 must have valid
non-zero values.
2. Set the PDN bit (Register 6, bit 3) and clear the PDL
bit (Register 6, bit 4).
3. The system-side module clock must stay active.
4. Reset the system-side module.
5. Program registers to the desired settings.
The Si306x also supports an additional powerdown
mode. When both the PDN (Register 6, bit 3) and PDL
(Register 6, bit 4) bits are set, the chipset enters a
complete powerdown mode and draws negligible
current (deep sleep mode). In this mode, the ring detect
function does not operate. Normal operation is restored
by the same process for taking the DAA out of sleep
mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI3062-F-FSR | 制造商:Silicon Laboratories Inc 功能描述:INTEGRATED DIRECT ACCESS ARRANGEMENT 16SOIC - Tape and Reel |
| SI3062-X-FS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE |
| SI3063 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE |
| Si3063-F-FS | 功能描述:電信線路管理 IC Enhanced V.92 Global Line-Side RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3063-F-FSR | 制造商:Silicon Laboratories Inc 功能描述:INTEGRATED DIRECT ACCESS ARRANGEMENT 16SOIC - Tape and Reel |
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