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Si306x
32
Rev. 0.9
Reset settings = 0000_0000
Register 4. Interrupt Source
Bit
D7
D6D5D4
D3D2
D1D0
Name
RDTI
ROVI
FDTI
BTDI
DODI
LCSOI
POLI
Type
R/W
Bit
Name
Function
7
RDTI
Ring Detect Interrupt.
0 = A ring signal is not occurring.
1 = A ring signal is detected. If the RDTM (Register 3) and INTE (Register 2) bits are set a hard-
ware interrupt occurs on the INT port. This bit must be written to a 0 to be cleared. The RDI bit
(Register 2) determines if this bit is set only at the beginning of a ring pulse, or at the end of a
ring pulse as well. This bit should be cleared after clearing the PDL bit (Register 6) because
powering up the line-side device may cause this interrupt to be triggered.
6ROVI
Receive Overload Interrupt.
0 = An excessive input level on the receive pin is not occurring.
1 = An excessive input level on the receive pin is detected. If the ROVM and INTE bits are set a
hardware interrupt occurs on the INT port. This bit must be written to 0 to clear it. This bit is iden-
tical in function to the ROV bit (Register 17). Clearing this bit also clears the ROV bit.
5FDTI
Frame Detect Interrupt
.
0 = Frame detect is established on the communications link.
1 = This bit is set when the communications link does not have frame lock. If the FDTM and
INTE bits are set, a hardware interrupt occurs on the INT port. Once set, this bit must be written
to a 0 to be cleared.
4BTDI
Billing Tone Detect Interrupt.
0 = A billing tone has not occurred.
1 = A billing tone has been detected. If the BTDM and INTE bits are set, a hardware interrupt
occurs on the INT port. This bit must be written to 0 to clear it.
3DODI
Drop Out Detect Interrupt
.
0 = The line-side power supply has not collapsed.
1 = The line-side power supply has collapsed. (The DOD bit in Register 19 has fired.) If the
DODM and INTE bits are set, a hardware interrupt occurs on the INT port. This bit must be writ-
ten to 0 to clear it. This bit should be cleared after clearing the PDL bit (Register 6) because
powering as the line-side device can cause this interrupt to be triggered.
2LCSOI
Loop Current Sense Overload Interrupt
.
0 = The LCS bits have not reached max (all ones).
1 = The LCS bits have reached max value. If the LCSOM bit (Register 3) and the INTE bit are
set, a hardware interrupt occurs on the INT port. This bit must be written to 0 to clear it.
LCSOI does not necessarily imply that an overcurrent situation has occurred. An overcurrent sit-
uation in the DAA is determined by the status of the OPD bit (Register 19). After the LCSOI
interrupt fires, the OPD bit should be checked to determine if an overcurrent situation exists.
1
Reserved Read returns zero.
0POLI
Polarity Reversal Detect Interrupt (Si3062, Si3063, and Si3065 line-side devices only).
0 = Bit 7 of the LVS register does not change states.
1 = Bit 7 of the LVS register changes from a 0 to a 1, or from a 1 to a 0, indicating the polarity of
TIP and RING is switched. If the POLM and INTE bits are set, a hardware interrupt occurs on
the INT port. To clear the interrupt, write this bit to 0.