參數(shù)資料
型號(hào): SI3062-F-FS
廠商: Silicon Laboratories Inc
文件頁數(shù): 43/62頁
文件大?。?/td> 0K
描述: IC DAA ENH FCC LINE-SIDE 16SOIC
標(biāo)準(zhǔn)包裝: 48
功能: 直接存取裝置(DAA)
電路數(shù): 1
電流 - 電源: 9mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC N
包裝: 管件
包括: 結(jié)帳音調(diào)檢測(cè),線路電壓監(jiān)視器,回路電流監(jiān)視器,過載檢測(cè),振鈴檢測(cè)器
Si306x
48
Rev. 0.9
Reset settings = 0001_1001
Register 24. Ring Validation Control 3
Bit
D7
D6
D5
D4D3D2D1D0
Name
RNGV
RAS[5:0]
Type
R/W
Bit
Name
Function
7RNGV
Ring Validation Enable.
0 = Ring validation feature is disabled.
1 = Ring validation feature is enabled in both normal operating mode and low-power
mode.
6
Reserved
Reserved and may read either a 1 or 0.
5:0
RAS[5:0]
Ring Assertion Time.
These bits set the maximum ring frequency for a valid ring signal within a 10% margin of
error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING
event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the
timer value is compared to the RMX[5:0] field and if it exceeds the value in RMX[5:0] then
the frequency of the ring is too high and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-
ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically
occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/
(2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency range [f_min,
f_max], the following equation should be used:
To compensate for error margin and ensure a sufficient ring detection window, it is recom-
mended that the calculated value of RMX[5:0] be incremented by 1.
RMX 5:0
[] RAS 5:0
[]
1
2 f_max
×
2 ms
×
--------------------------------------------- RMX RAS
,
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