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參數(shù)資料
| 型號： | SI3062-F-FS |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 13/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAA ENH FCC LINE-SIDE 16SOIC |
| 標準包裝： | 48 |
| 功能： | 直接存取裝置（DAA） |
| 電路數(shù)： | 1 |
| 電流 - 電源： | 9mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC N |
| 包裝： | 管件 |
| 包括： | 結帳音調(diào)檢測，線路電壓監(jiān)視器，回路電流監(jiān)視器，過載檢測，振鈴檢測器 |
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Si306x
20
Rev. 0.9
The 8-bit LCS2 register also reports loop current in the
off-hook state. This register has resolution of 1.1 mA/bit.
6.12. Off-Hook
The system generates an off-hook command by setting
the OH bit (Register 5, bit 0). With the OH bit set, the
system is in an off-hook state. The off-hook state seizes
the line for incoming/outgoing calls and also can be
used for pulse dialing. When the DAA is on-hook,
negligible dc current flows through the hookswitch.
When the DAA is placed in the off-hook state, the
hookswitch transistor pair, Q1 and Q2, turn on. A
termination impedance across TIP and RING is applied
and causes dc loop current to flow. The termination
impedance has an ac and dc component.
Several events occur in the DAA when the OH bit is set.
There is a 250
s latency to allow the off-hook
command to be communicated to the line-side device.
Once the line-side device goes off-hook, an off-hook
counter forces a delay before transmission or reception
occurs for line transients to settle. This off-hook counter
time
is
controlled
by
the
FOH[1:0]
bits
(Register 31, bits 6:5). The default setting for the off-
hook counter time is 128 ms, but can be adjusted up to
512 ms or down to either 64 or 8 ms.
After the off-hook counter has expired, a resistor
calibration is performed for 17 ms. This allows circuitry
internal to the DAA to adjust to the exact conditions
present at the time of going off-hook. This resistor
calibration can be disabled by setting the RCALD bit
(Register 25, bit 5).
After the resistor calibration is performed, an ADC
calibration is performed for 256 ms. This calibration
helps to remove offset in the A/D sampling the
telephone line. This ADC calibration can be disabled by
setting the CALD bit (Register 17, bit 5). See “6.6.
Calibration” on page 17. for more information on
automatic and manual calibration.
Silicon Labs recommends that the resistor and the ADC
calibrations not be disabled except when a fast
response is needed after going off-hook, such as when
responding to a Type II caller-ID signal. See “6.24.
To calculate the total time required to go off-hook and
start transmission or reception, the digital filter delay
should be included in the calculation. (Refer to Table 4
in the appropriate embedded system-side DAA module
specification to calculate the digital FIR filter group
delay.)
6.13. Interrupts
The INT port in the system-side module can be used by
setting the INTE bit (Register 2, bit 7). The default state
of this interrupt output port is active low, but active high
operation can be enabled by setting the INTP bit
(Register 2, bit 6). Bits 7–2, and 0 in Register 3 and bit 1
in Register 44 can be set to enable hardware interrupt
sources. When one or more of these bits are set, the
INT port becomes active and stays active until the
interrupts are serviced. If more than one hardware
interrupt is enabled in Register 3, software polling
determines the cause of the interrupts. Register 4 and
bit 3 of Register 44 contain sticky interrupt flag bits.
Clear these bits after servicing the interrupt.
Registers 43 and 44 contain the line current/voltage
threshold interrupt. These line current/voltage registers
and interrupts are only available with the Si3063 and
Si3064 line-side devices. This interrupt will trigger when
either the measured line voltage or current in the LVS or
LCS2 registers, as selected by the CVS bit (Register 44,
bit 2), crosses the threshold programmed into the
CVT[7:0] bits. An interrupt can be programmed to occur
when the measured value rises above or falls below the
threshold. Only the magnitude of the measured value is
used to compare to the threshold programmed into the
CVT[7:0] bits, and thus only positive numbers should be
used as a threshold. This line current/voltage threshold
interrupt is only available with the Si3063 and Si3064
line-side devices.
6.14. DC Termination
The DAA has programmable settings for dc impedance,
minimum operational loop current, and TIP/RING
voltage. The dc impedance of the DAA is normally
represented with a 50
slope as shown in Figure 5, but
can be changed to an 800
slope by setting the DCR
bit. This higher dc termination presents a higher
resistance to the line as loop current increases.
Table 9. Loop Current Transfer Function
LCS[4:0]
Condition
00000
Insufficient
line
current
for
normal
operation. Use the DOD bit (Register 19,
bit 1) to determine if a line is connected.
00100
Minimum line current for normal operation.
11111
Loop current may be excessive. Use the
OPD bit to determine if an overload condi-
tion exists.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SI3062-F-FSR | 制造商:Silicon Laboratories Inc 功能描述:INTEGRATED DIRECT ACCESS ARRANGEMENT 16SOIC - Tape and Reel |
| SI3062-X-FS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE |
| SI3063 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE |
| Si3063-F-FS | 功能描述:電信線路管理 IC Enhanced V.92 Global Line-Side RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3063-F-FSR | 制造商:Silicon Laboratories Inc 功能描述:INTEGRATED DIRECT ACCESS ARRANGEMENT 16SOIC - Tape and Reel |
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