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參數(shù)資料
| 型號： | SCAN926260TUF |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
| 中文描述： | HEX LINE RECEIVER, PBGA196 |
| 封裝： | LBGA-196 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 372K |
| 代理商： | SCAN926260TUF |
Initialization
(Continued)
Step 1: After applying power to the Deserializer, the outputs
are held high and the on-chip Power-on Reset (POR) cir-
cuitry disables the internal circuits. When V
cc
reaches V
cc
OK
(2.1V), the PLL in each deserializer begins locking to the
local clock (REFCLK). A local on-board oscillator or other
source that provides the specified clock input to the REFCLK
pin.
Step 2: The Deserializer PLL must synchronize to the Seri-
alizer to complete the initialization. Refer to the Serializer
data sheet for proper operation during the Initialization State.
The Deserializer identifies the rising clock edge in a synchro-
nization pattern or pseudo-random data and after 80 clock
cycles will synchronize to the data stream from the Serial-
izer. At the point where the Deserializer’s PLL locks to the
embedded clock, the LOCKn pin goes low and valid data
appears at the outputs.
Data Transfer
After initialization, the Serializer transfers data to the Dese-
rializer. The serial data stream includes a start and stop bit
appended by the serializer, which frames the ten data bits.
The start bit is always high and the stop bit is always low.
The start and stop bits also function as clock bits embedded
in the serial stream.
The Serializer transmits the data and clock bits (10+2 bits) at
12 times the TCLK frequency. For example, if TCLK is 40
MHz, the serial rate is 40 X 12 = 480 Mbps. Since only 10
bits are from input data, the serial ’payload’ rate is 10 times
the TCLK frequency. For instance, if TCLK = 40 MHz, the
payload data is 40 X 10 = 400 Mbps. TCLK is provided by
the data source and must be in the range of 16MHz to
66MHz.
When one of six Deserializer channels synchronizes to the
input from a Serializer, it drives its LOCKn pin low and
synchronously delivers valid data at its outputs. The Deseri-
alizer locks to the embedded clock, uses it to generate
multiple internal data strobes, and drives the embedded
clock to the RCLKn pin. The RCLKn pin is synchronous to
the data on the ROUTn[0:9] pins. While LOCKn is low, data
on ROUTn[0:9] is valid. Otherwise, ROUTn[0:9] and RCLKn
are high.
All ROUT, LOCK, and RCLK signals will drive a minimum of
three CMOS input gates (15pF load) with a 66 MHz clock.
This amount of drive allows bussing outputs of two Deseri-
alizers and a destination ASIC. REN controls TRI-STATE of
all the outputs.
The Deserializer input pins are high impedance during Pow-
erdown (PWRDNn or MS_PWRDN low) and power-off (V
cc
=
0V).
Resynchronization
Whenever one of the six Deserializers loses lock, it will
automatically try to resynchronize. For example, if the em-
bedded clock edge is not detected two times in succession,
the PLL loses lock and the LOCKn pin is driven high. The
system must monitor the LOCKn pin to determine when data
is valid.
The user has the choice of allowing the deserializer to re-
sync to the data stream or to force synchronization by as-
serting the Serializer SYNC1 or SYNC2 pin high. This
scheme is left up to user discretion. One recommendation is
to provide a feedback loop using the LOCKn pin itself to
control the sync request of the Serializer (SYNC1 or
SYNC2). Dual SYNC pins are provided for local or remote
control..
Powerdown
The Powerdown state is a low power sleep mode that the
Deserializer typically occupies while waiting for initialization
or to reduce power consumption when no data is transferred.
While in Powerdown Mode, the PLL stops and RCLK and
ROUTn[0:9] are high, which reduces the supply current for
each channel by approximately 80mA. Each channel has a
powerdown (PWRDWNn) pin that puts the respective chan-
nel into sleep mode when asserted low. In addition, the
SCAN926260 has a master powerdown (MS_PWRDWN)
pin that overrides each individual powerdown pin and puts
the entire device into sleep mode when asserted low (This
same condition can be replicated by asserting all six indi-
vidual powerdown pins low.). The powerdown pins are inter-
nally pulled low which defaults the device into sleep mode.
Active operation requires asserting a high on MS_PWRDWN
and the selected channel’s PWRDWNn pin.
Upon exiting Powerdown, the Deserializer enters the Initial-
ization state. The system must then allow time to Initialize
before data transfer can begin.
TRI-STATE
When the system drives the REN pin low, the Deserializer
enters TRI-STATE. This will TRI-STATE the receiver output
pins (ROUTn[0:9]) and RCLK[0:5]. When the system drives
REN high, the Deserializer will return to the previous state as
long as all other control pins remain static (PWRDWNn,
MS_PWRDWN). The LOCKn pin is not affected by REN and
continues to be active, signalling LOCK status. This allows
the system to be sure the channel is locked before enabling
the data outputs.
S
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SCAN926260TUF/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN926260TUFX | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN926260TUFX/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN928028 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST |
| SCAN928028TUF | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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