參數(shù)資料
型號: SCAN926260TUF
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST
中文描述: HEX LINE RECEIVER, PBGA196
封裝: LBGA-196
文件頁數(shù): 10/18頁
文件大?。?/td> 372K
代理商: SCAN926260TUF
SCAN926260 Control Signal Truth Table
SCAN Mode Internal Signals
SCAN_HIZB
INPUTS
PWRDWN[n]
OUTPUTS
ROUTn[0:9]
STATE
SCAN
(Note 1)
SCAN
(Note 1)
Powerdown
(Note 2)
Powerdown
(Note 3)
Normal,
Not Locked
(Note 5)
Normal,
Locked
(Note 5)
REN = Low,
Not Locked
(Note 4, 6)
REN = Low,
Locked
(Note 4, 6)
SCAN_BIST
MS_PWRDWN
REN
LOCK[n]
RCLK[n]
0
X
X
X
X
Z
10
@
Z
Z
1
1
X
X
X
Z
10
@
Z
Z
1
0
0
X
X
1
10
@
1
1
1
0
1
All 6
@
0
X
1
10
@
1
1
1
0
1
1
1
1
10
@
1
1
1
0
1
1
1
0
data
clock
1
0
1
1
0
1
10
@
Z
Z
1
0
1
1
0
0
10
@
Z
Z
Default State (Note 6)
0
0
0
1
10
@
1
1
Key:
Z = High Impedance
X = Don’t Care
10
@
Z = All 10 ROUT for the respective Channel are High Impedance
1 = High Voltage Level
0 = Low Voltage Level
SCAN_HIZB = the internal control signal from the HighZ command at the TAP Controller
SCAN_BIST = the internal control signal from the BIST command at the TAP Controller
Notes:
1) JTAG/SCAN has the highest priority. SCAN_HIZB is active low and SCAN_BIST is active high. If either control is active, the outputs will be in TRI-STATE.
2) MS_PWRDWN has the second highest priority. When MS_PWRDWN is low, the entire chip enters sleep mode and all outputs (ROUTn[0:9], RCLK[n], and
LOCK[n]) are high.
3) PWRDWN[n] are the six individual power-down pins. Each will power down the respective channel. A special case occurs when all six PWRDWN[n] pins are
low-the common bias circuits will also be powered down. This state is equivalent to the case when MS_PWRDWN is low.
4) REN has a lower priority than PWRDWN[n]. When REN is low, the output data (ROUTn[0:9] and RCLK[n]) will be in TRI-STATE. The LOCK[n] signal’s output is
not affected by REN.
5) During normal operation mode (no SCAN, no Power-down, and REN high), LOCK[n] controls the ROUTn[0:9] and RCLK[n] outputs. When LOCK[n] is high
(unlocked), all outputs will be 1, and when LOCK[n] is low (locked), both data and clock will be valid at the outputs. BIST-ALONE mode is considered part of normal
operation and can be overriden by any of the above priorities.
6) There are internal pull-downs on the REN, PWRDWNn and MS_PWRDWN pins. Active operation requires asserting these pins high.
S
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