參數(shù)資料
型號: SCAN926260TUF
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST
中文描述: HEX LINE RECEIVER, PBGA196
封裝: LBGA-196
文件頁數(shù): 4/18頁
文件大?。?/td> 372K
代理商: SCAN926260TUF
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise
specified. (Note 2) (Continued)
Symbol
Parameter
Conditions
Pin/Freq.
66MHz
16MHz
66MHz
16MHz
Min
400
1.3
440
1.4
Typ
500
2.51
600
2.59
Max
Units
ps
ns
ps
ns
t
RNMI-RIGHT
Deserializer Right
Noise Margin
Figure 8
(Note 8)
t
RNMI-LEFT
Deserializer Left
Noise Margin
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2:
Typical values are given for VDD = 3.3V and TA =25C
Note 3:
Current into the device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VTH and
VTL which are differential voltages.
Note 4:
Total Supply Current when Powered Down (I
CCXR
) is higher than previous six channel devices because previous devices asserted ROUTn and RCLKn into
TRI-STATE upon loss-of-lock, whereas the SCAN926260 now asserts ROUTn and RCLKn HIGH upon loss-of-lock.
Note 5:
t
RDC
was specified by measuring the positive pulse on the RCLK and dividing this number by the ideal pulse width.
Note 6:
t
CLH
and t
CHL
are Guranteed by Statistical Analysis (GBSA). Please see
Figure 3
for a graphical representation.
Note 7:
For the purpose of specifying deserializer PLL performance, t
DSR1
and t
DSR2
are specified with the REFCLK running and stable, and specific conditions of
the incoming data stream (SYNCPATs). t
DSR1
is the time required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. t
DSR2
is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI) conditions change from not receiving data to receiving
synchronization patterns (SYNCPATs). The time to lock to random data is dependent upon the incoming data and is not specified.
Note 8:
t
RNMI-LEFT
and t
RNMI-RIGHT
are a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur.
The Deserializer noise margin specification does not include transmitter jitter and is Guaranteed By Statistical Analysis (GBSA). Please see
Figure 8
for a graphical
representation.
SCAN Circuitry Timing Requirements
Symbol
f
MAX
Parameter
Conditions
Min
25.0
Typ
50.0
Max
Units
MHz
Maximum TCK Clock
Frequency
TDI to TCK, H or L
TDI to TCK, H or L
TMS to TCK, H or L
TMS to TCK, H or L
TCK Pulse Width, H or L
TRST Pulse Width, L
Recovery Time, TRST to
TCK
R
L
= 500
, C
L
= 35 pF
t
S
t
H
t
S
t
H
t
W
t
W
t
REC
2.0
1.0
2.5
1.0
10.0
2.5
2.0
ns
ns
ns
ns
ns
ns
ns
S
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