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參數(shù)資料
| 型號： | SCAN926260TUF |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
| 中文描述： | HEX LINE RECEIVER, PBGA196 |
| 封裝： | LBGA-196 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 372K |
| 代理商： | SCAN926260TUF |
Application Information
(Continued)
where use of the individual channel is well known or con-
trolled, using the respective channel’s PWRDWNn pin(s)
may eliminate the need for external Failsafe Biasing. Please
see
Figure 11
for the Failsafe Biasing Setup.
DIFFERENCES BETWEEN the DS92LV1260, the
SCAN921260, and the SCAN926260
The DS92LV1260 is a six channel, ten bit, Bus LVDS Dese-
rializer with random lock capability and a parallel clock rate
up to 40MHz. Each channel contains a recovered clock
(RCLKn) and lock (LOCKn) output. The DS92LV1260 also
contains a seventh serial input channel that serves as a
redundant input. Also, unlike previous deserializers, the
LOCKn signal is synchronous to valid data appearing on the
outputs. Please see the DS92LV1260 datasheet for more
specific details about the seventh redundant channel and
further details.
The SCAN921260 contains the same basic functions as the
DS92LV1260. However, the SCAN921260 has an increased
parallel clock rate up to 66MHz, is IEEE 1149.1 (JTAG)
compliant and also contains at-speed Built-In-Self-Test
(BIST).
The SCAN926260 contains the same basic functions as the
SCAN921260. However, in addition to a master powerdown,
the SCAN926260 has individual powerdown pins per chan-
nel, has eliminated the seventh redundant channel, and now
asserts all outputs ROUTn[0:9] and RCLKn high during pow-
erdown and during loss of lock. Please also note that the
LOCKn pin output is no longer affected by REN. Also, the
SCAN926260 is footprint compatible and may be used inter-
changibly with the SCAN921260.
USING NOISE MARGIN TO VALIDATE SIGNAL
QUALITY
The parameters t
and t
are calculated by
first measuring how much of the ideal bit the receiver needs
to ensure correct sampling. After determining this amount,
what remains of the ideal bit that is available for external
sources of noise is called noise margin. Noise margin does
not include transmitter jitter. Please see
Figure 8
for a
graphical explanation. Also, for a more detailed explanation
of noise margin, please see Application Note 1217 titled
"How to Validate BLVDS SER/DES Signal Integrity Using an
Eye Mask."
The vertical limits of the mask are determined by the
SCAN926260 receiver input threshold of
±
50mV.
BYPASS
Circuit board layout and stack-up for the BLVDS devices
should be designed to provide noise-free power to the de-
vice. Good layout practice will also separate high-frequency
or high-level inputs and outputs to minimize unwanted stray
noise pickup, feedback and interference. Power system per-
formance may be greatly improved by using thin dielectrics
(4 to 10 mils) for power / ground sandwiches. This increases
the intrinsic capacitance of the PCB power system which
improves power supply filtering, especially at high frequen-
cies, and makes the value and placement of external bypass
capacitors less critical. External bypass capacitors should
include both RF ceramic and tantalum electrolytic types. RF
capacitors may use values in the range of 0.01 uF to 0.1 uF.
Tantalum capacitors may be in the 2.2 uF to 10 uF range.
Voltage rating of the tantalum capacitors should be at least
3X the power supply voltage being used.
It is a recommended practice to use two vias at each power
pin as well as at all RF bypass capacitor terminals. Dual vias
reduce the interconnect inductance by up to half, thereby
reducing interconnect inductance and extending the effec-
tive frequency range of the bypass components. Locate RF
capacitors as close as possible to the supply pins, and use
wide low impedance traces (not 50 Ohm traces). Surface
mount capacitors are recommended due to their smaller
parasitics. When using multiple capacitors per supply pin,
locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low
frequency switching noise.
Some devices provide separate power and ground pins for
different portions of the circuit. This is done to isolate switch-
ing noise effects between different sections of the circuit.
Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some
cases, an external filter may be used to provide clean power
to sensitive circuits such as PLL circuitry.
Use at least a four layer board with a power and ground
plane. Locate CMOS (TTL) signals away from the LVDS
lines to prevent coupling. Closely-coupled differential lines of
100 Ohms Z
are typically recommended for LVDS inter-
connects. The closely-coupled lines help to ensure that
coupled noise will appear as common-mode and is rejected
by the receivers. Also, the tight coupled lines will radiate
less.
Termination of the LVDS interconnect is required. For point-
to-point applications, termination should be located at the
load end. Nominal value is 100 Ohms to match the line’s
differential impedance. Place the resistor as close to the
receiver inputs as possible to minimize the resulting stub
between the termination resistor and receiver.
Additional general guidance can be found in the LVDS Own-
er’s Manual - available in PDF format from the national web
site at: www.national.com/lvds. For packaging information on
BGA’s, please see AN-1126.
Guidance for the SCAN926260 is provided next:
SCAN926260: SIX 1 TO 10 DESERIALIZERS
General guidance is provided below. Exact guidance can not
be given as it is dictated by other board level /system level
criteria. This includes the density of the board, power rails,
power supply, and other integrated circuit power supply
needs.
DVDD = DIGITAL SECTION POWER SUPPLY
These pins supply the digital portion and receiver output
buffers of the device. Receiver DVDD pins require more
bypass to power outputs under synchronous switching con-
ditions.An estimate of local capacitance requires a minimum
of 20nF. This is calculated by taking 66 (60 LVTTL Outputs +
6 RCLK Outputs) times the maximum output short circuit
current (IOS) of 85mA. Multiplying this number by the maxi-
mum rise time (t
) of 4ns and dividing by the maximum
allowed droop in VDD (assume 50mV) yields 448.8nF. Di-
viding this number by the number of DVDD pins (25) yields
18nF. Rounding up to a standard value, 0.1uF is selected for
each DVDD pin. The capacitative bandwidth for this capaci-
tor may be extended by placing a 0.01uF capacitor in paral-
lel. The 0.01uF capacitor should be placed closer to the
DVDD pin than the 0.1uF capacitor.
S
www.national.com
13
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PDF描述 |
|---|---|
| SCAN926260TUFX | Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
| SCAN928028 | 8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST |
| SCAN928028TUF | 8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST |
| SCAN928028TUFX | 8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST |
| SCAN92LV090 | 9 Channel Bus LVDS Transceiver with 1149.1 Access |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCAN926260TUF/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN926260TUFX | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN926260TUFX/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN928028 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST |
| SCAN928028TUF | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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