參數(shù)資料
型號: SCAN926260TUF
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST
中文描述: HEX LINE RECEIVER, PBGA196
封裝: LBGA-196
文件頁數(shù): 16/18頁
文件大小: 372K
代理商: SCAN926260TUF
Pin Descriptions
Pin Name
Type
GND
Bus LVDS
Input
Pins
Description
GND
B2, B14, L4, L5
A3-A4, A6-A7, A9-10,
C5-C6, C8-C9, C10-C11
Ground pins for ESD structures.
Bus LVDS differential input pins. Failsafe described in
Application Information section.
This pin is not bonded out. Therefore, you may tie this pin
High, Low, or as a N/C. However, for board layout
compatibility with the SCAN921260 or the DS92LV1260, tie
this pin LOW.
R
INn
±
N/C
E3
DVdd
B1, B3, C4, D6, D12, E6,
E7, E9, E10, F7, F10,
F12, G6, G10, H6, H10,
J5, J8, J9, J10, K5, K6,
K7, K10, L10
A1, D4, D5, D7, D9, D11,
E5, E8, F5, F6, F8, F9,
G5, G7, G8, G9, H5, H7,
H8, H9, J6, J7, K8, K9, L7
E1, F1, F14, G14, J1, J14,
K1, K14,P5, P6, P9, P10
A14, B12, D10, G1, G2,
G13, H1, H13, H14, J4,
J13, N7, N8, P7, P8
A11, B6, B9, C7
A5, A8, B7, B8, B11
Supply voltage for digital section.
DGND
Ground pins for digital section.
PVdd
Supply voltage for PLL circuitry.
PGND
Ground pins for PLL circuitry.
AVdd
AGND
Supply voltage for analog circuitry.
Ground pins for analog circuitry.
A low on one of these pins puts the corresponding channel
into sleep mode and a high makes the corresponding channel
active. There is an internal pull-down on each of these pins
that defaults the PWRDWNn input to sleep mode. Active
operation requires asserting a high on the PWRDWNn and
MS_PWRDWN input.
A low on this pin puts the device into sleep mode and a high
makes the part active. There is an internal pull-down that
defaults the MS_PWRDWNn input to sleep mode. Active
operation requires asserting a high on the MS_PWRDWNn
input.
Enables the ROUTn[0:9], RCLKn, outputs. There is an internal
pull-down that defaults REN to TRI-STATE the outputs. Active
outputs require asserting a high on REN. Please note that
LOCKn is not affected by REN.
Frequency reference input. Used by the PLL while locking
onto incoming LVDS streams.Has no phase relation to RCLK.
Indicates the status of the PLLs for the individual deserializers:
LOCKn= L indicates locked, LOCKn= H indicates unlocked.
PWRDWN [0:5]
3.3V CMOS
Input
A12, A13, C3, C12, E11,
F11
MS_PWRDWN
3.3V CMOS
Input
B5
REN
3.3V CMOS
Input
A2
REFCLK
3.3V CMOS
Input
3.3V CMOS
Output
B4
LOCK[0:5]
D13, F3, N3, P1, P12,
P13
S
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相關PDF資料
PDF描述
SCAN926260TUFX Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST
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SCAN928028TUF 8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST
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SCAN926260TUFX 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel
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