參數(shù)資料
型號： SC2000
廠商： NXP SEMICONDUCTORS
元件分類： 路由/交換
英文描述： Universal Timeslot Interchange
中文描述： TELECOM, DIGITAL TIME SWITCH, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 9/44頁
文件大小： 221K
代理商： SC2000
2000 Sep 07
9
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Reset (CS_7):
Setting this bit to 1 forces
the SC2000 into its reset state, and
initializes all internal registers. This
command reproduces the function
of the RESET pin. Setting this bit to 0
returns the SC2000 to normal operation.
This bit can be read back for verification
purposes.
Internal Registers
The internal registers are accessed by
reads and writes to the Data Registers
using the address held in the Internal
Address Register.
Internal Register Memory Map
Values for
A_7 .. A_0 (H)
Function
R/W
00
.
.
03
Configuration 1
.
.
Configuration 4
R/W
04
Version/Revision
R/W
05
.
.
7F
Reserved
.
.
Reserved
R/W
80
.
.
9F
Destn Routing
.
.
Destn Routing
R/W
A0
.
.
BF
Source Routing
.
.
Source Routing
R/W
C0
.
.
DF
Destn Parallel
.
.
Destn Parallel
R/W
E0
.
.
FF
Source Parallel
.
.
Source Parallel
R/W
Configuration Registers
Configuration Register 1(00H)
Global Output Enable (C_0):
Clearing
this bit to 0 forces all outputs to the high
impedance state, with the exception of
the microprocessor interface data bus.
Setting this bit to 1 enables all outputs.
This bit is cleared on RESET.
Expansion Bus Timing Driver
Enable (C_1):
When SCbus Mode is
selected (C_4 = 0), clearing this bit to
0 disables the expansion bus timing
drivers.
When PEB Resource Mode is selected
(C_6, C_4 = 01), this bit has no effect.
When PEB Network Mode is selected
(C_6, C_4 = 11), clearing this bit to 0
disables the expansion bus drivers
CLKR, L_CLKT, FSYNCR, L_FSYNCT,
MSYNCR, and L_MSYNCT. Setting this
bit to 1 enables these timing drivers.
This bit is cleared on RESET.
Framing Mode (C_3, C_2):
This two-bit
field selects the number of bits per frame
(B/F), time slots per frame (TS/F) and
frames per multi-frame (F/MF) on both
the local and expansion bus.
When SCbus Mode is selected
(C_4 = 0), there is no multi-frame sync
signal available on the expansion bus.
The (00) combination of (C_3, C_2)
is invalid. In this case the internal
multi-frame sync will be free running,
and synchronous to FSYNC.
When PEB Mode is selected (C_4 = 1)
the only valid combinations of (C_3,
C_2) are (00) and (01).
These bits are cleared on RESET.
Expansion Bus Interface Select (C_4):
This bit selects the expansion bus inter-
face operating mode. Clearing this bit to
0 selects SCbus Mode. Setting this bit to
1 selects PEB Mode.
This bit is cleared on RESET.
Configuration Register 1
BIT
Function
0
C_0: Global Output Enable
1
C_1: Expansion Bus Timng
Driver Enable
2
3
C_2: Framng Mode 0
C_3:Framng Mode 1
4
C_4: Expansion Bus
Interface Select
5
C_5: SCbus Loopback Mode
6
7
C_6: PEB module Type 0
C_7:PEB Module Type 1
Note:
Bit 0 is the LSB of the Low Byte
Data Register.
Expansion Bus
C_3, C_2
B/F
TS/F
F/MF
00
193
24
12
01
256
32
16
10
512
64
16
11
1024
128
16
Local Bus
C_3, C_2
B/F
TS/F
F/MF
00
193
24
12
01
256
32
16
10
256
32
16
11
256
32
16
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