參數(shù)資料
型號(hào)： SC2000
廠商： NXP SEMICONDUCTORS
元件分類： 路由/交換
英文描述： Universal Timeslot Interchange
中文描述： TELECOM, DIGITAL TIME SWITCH, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 13/44頁(yè)
文件大?。?/td> 221K
代理商： SC2000
2000 Sep 07
13
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Time Slot Select (DR_6 .. DR_0):
This
7-bit field specifies a time slot number
between 0 and 127. DR_6 is the MSB of
this field.
Port Select (DR_11 .. DR_8):
When
SCbus mode is selected (C_4 = 0) this
4-bit field specifies an SCbus data
stream number between 0 and 15.
DR_11 is the MSB of this field.
When a PEB Mode with switching is
selected (C_6, C_4 = 11) this 4- bit field
specifies a PEB data stream. See table for
details.
Destination Routing Memory LSB
Bit
Function
0
1
2
3
4
5
6
DR_0: Time slot Select 0
DR_1: Time slot Select 1
DR_2: Time slot Select 2
DR_3: Time slot Select 3
DR_4: Time slot Select 4
DR_5: Time slot Select 5
DR_6: Time slot Select 6
7
DR_7: Reserved
Note:
Bit 0 is the LSB of the Low Byte
Data Register.
Destination Routing Memory MSB
Bit
Function
0
1
2
3
DR_8: Port Select 0
DR_9: Port Select 1
DR_10: Port Select 2
DR_11: Port Select 3
4
DR_12: Reserved
5
DR_13: Reserved
6
DR_14: Parallel Access Enable
7
DR_15: Switch Output Enable
Note:
Bit 0 is the LSB of the High Byte
Data Register.
Parallel Access Enable (DR_14):
When
this bit is cleared to 0, the SC2000 uses
the local SI bus as the source of data
for the expansion bus. When this bit is
set to 1 the SC2000 uses the contents of
the corresponding Destination Parallel
Access Register as the source of expan-
sion bus data.
Switch Output Enable (DR_15):
When
this bit is cleared to 0, the SC2000 ex-
pansion bus drivers are forced to the
high impedance state during the speci-
fied time slot period. When this bit is set
to 1 the SC2000 expansion bus drivers
drive the bus during the specified time
slot period.
Source Routing Memory (A0H - BFH):
The Source Routing Memory maps time
slots from the expansion bus onto time
slots on the local SO bus. Each location
in the Source Routing Memory
corresponds to a time slot on the
local SO bus.
Destination Port Select (PEB Mode)
DR_11..DR_8
PEB Destination
0H
L_SERT/L_TSX*
1H
SERR
2H
R_SERT/R_TSX*
3H
SERT
4H
.
.
FH
Reserved
.
.
Reserved
Source Routing Memory
IAR
Source Mapping
A0H
Channel 0
A1H
Channel 1
A2H
Channel 2
.
.
.
.
BFH
Channel 31
Note:
IAR
= Internal Address register contents.
Channel N
is equivalent to time slot N
on the local S0 bus.
The contents of all Source Routing
Memory Location are cleared on
RESET.
When writing data into the Source
Routing Memory the Low Byte Data
Register contains a 7-bit binary field
holding a time slot number, and the
High Data Byte Register contains a 4-bit
binary field holding a Port (stream)
number. Together these two fields
uniquely identify a time slot on the
expansion bus which will be used as a
source of data for a time slot on the local
SO bus.
Time slot Select (SR_6 .. SR_0):
This
7-bit field specifies a time slot number
between 0 and 127. SR_6 is the MSB of
this field.
Port Select (SR_11 .. SR_8):
When
SCbus Mode is selected (C_4 = 0),
this 4-bit field specifies an SCbus data
stream number between 0 and 15.
SR_11 is the MSB of this field.
When a PEB Mode with switching is
selected (C_6, C_4 = 11) this 4-bit field
specifies a PEB data stream as follows:
Source Routing Memory LSB
Bit
Function
0
1
2
3
4
5
6
SR_0: Time Slot Select 0
SR_1: Time Slot Select 1
SR_2: Time Slot Select 2
SR_3: Time Slot Select 3
SR_4: Time Slot Select 4
SR_5: Time Slot Select 5
SR_6: Time Slot Select 6
7
SR_7: Reserved
Note:
Bit 0 is the LSB of the Low Byte
Data Register.
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