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參數(shù)資料
| 型號(hào)： | SC2000 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 路由/交換 |
| 英文描述： | Universal Timeslot Interchange |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 19/44頁 |
| 文件大?。?/td> | 221K |
| 代理商： | SC2000 |
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2000 Sep 07
19
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Table 3.
Local Bus Interface Timing — SCbus Mode (2.048 Mbps)
Symbol
Parameter
Mn
Typ
Max
Unit
t1
SCLKx2*low time
122
ns
t2
SCLKx2*high time
122
ns
t3
SCLKx2*period
244
ns
t4
SCLK low time
244
ns
t5
SCLK high time
244
ns
t6
SCLK period
488
ns
t7
FSYNC*setup to SCLK
↑
0
ns
t8
FSYNC*hold fromSCLK
↑
15
ns
t9
SI_CLK
↓
delay fromSCLKx2*
↓
40
ns
t10
SI_CLK
↑
delay fromSCLKx2*
↑
40
ns
t11
SO_CLK
↑
delay fromSCLK
↑
40
ns
t12
SO_CLK
↓
delay fromSCLK
↓
40
ns
t13
SI_FS, SI_MS
↓
delay fromSCLKx2*
↑
45
ns
t14
SI_FS, SI_MS
↑
delay fromSCLKx2*
↑
45
ns
t15
SO_FS, SO_MS
↑
delay fromSCLK
↑
45
ns
t16
SO_FS, SO_MS
↓
delay fromSCLK
↑
45
ns
t17
SO float to valid delay fromSCLK
↑
40
ns
t18
SO valid to valid delay fromSCLK
↑
40
ns
t19
SO valid to float delay fromSCLK
↑
25
ns
t20
SI setup to SCLK
↓
(50% sample position)
0
ns
t21
SI hold fromSCLK
↓
(50% sample position)
25
ns
t22
SI setup to SCLKx2*
↑
(75% sample position)
0
ns
t23
SI hold fromSCLKx2*
↑
(75% sample position)
25
ns
t24
SD_[15:0] float to valid delay fromSCLK
↑
35
ns
t25
SD_[15:0] valid to valid delay fromSCLK
↑
35
ns
t26
SD_[15:0] valid to float delay fromSCLK
↑
25
ns
t27
SD_[15:0] setup to SCLK
↓
(50% sample)
0
ns
t28
SD_[15:0] hold fromSCLK
↓
(50% sample)
25
ns
t29
SD_[15:0] setup to SCLKx2*
↑
(75% sample)
0
ns
t30
SD_[15:0] hold fromSCLKx2*
↑
(75% sample)
25
ns
t31
TXD setup to SCLK
↑
(registered MC)
0
ns
t32
TXD hold fromSCLK
↑
(registered MC)
25
ns
t33
MC delay fromSCLK
↑
(registered MC)
85
ns
t34
MC delay fromTXD (passed through MC
80
ns
t35
RXD delay fromMC
35
ns
Notes:
1. Timng measured with 100 pF load on all Local Bus outputs, 200 pF load on all SCbus outputs.
2. MC timng measured with 200 pF, 470
pullup (4.7 K
/10). Open collector low to high transitions include 61 ns delay fromhi-Z to 2.4 V.
3. SI_CLK, SI_FS and SI_MS shown in ST-BUS framng format. When in PEB conventional framng format SI_CLK, SI_FS and SI_MS have
identical timng to SO_CLK, SO_FS and SO_MS.
4. SO shown configured as tri-state driver.
5. SO_MS, SI_MS are free-running multi-frame synchronization signals that occur once every 16 frames.
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