參數(shù)資料
型號(hào): SC2000
廠商: NXP SEMICONDUCTORS
元件分類: 路由/交換
英文描述: Universal Timeslot Interchange
中文描述: TELECOM, DIGITAL TIME SWITCH, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 5/44頁(yè)
文件大小: 221K
代理商: SC2000
2000 Sep 07
5
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Additional Features
The SO output may be set to high im-
pedance on frame boundaries by setting
the Source Routing Memory Switch
Output Enable Bit. This allows outputs
from multiple devices to be connected
to a common line. The SO signal may
also be configured as an open collector
output.
The data sample position of both local
and external buses is selectable between
50% and 75% of the bit width.
Logical and Physical Pinout Diagrams
SC2000
D_7
D_6
D_5
D_4
D_3
D_2
D_1
D_0
A_1
A_0
CS*
RD*(STRB*)
WR*(R/W*)
RESET
I*(M)
PLCC68
INT
(CLKT) SCLKX2*
(FSYNCT) SCLK
(MSYNCT) RSRVD
(SERT) FSYNC*
(SIGT) CLKFAIL
(L_CLKT) SD_0
(L_FSYNCT) SD_1
(L_MSYNCT) SD_2
(L_TSX*) SD_3
(L_SERT) SD_4
(L_SIGT) SD_5
(CLKR) SD_6
(FSYNCR) SD_7
(MSYNCR) SD_8
(SERR) SD_9
(SIGR) SD_10
(R_CLKT) SD_11
(R_FSYNCT) SD_12
(R_MSYNCT) SD_13
(R_TSX*) SD_14
(R_SERT) SD_15
(R_SIGT) MC
SO_CLK
SI_CLK
SO_FS
SI_FS
SO_MS
SI_MS
SO
RXD
35
55
57
58
59
61
62
63
65
66
67
1
3
4
5
7
8
9
11
12
13
15
16
41
40
48
47
46
44
43
53
24
26
27
29
30
31
32
33
37
38
23
22
20
18
17
50
52
39
54
CLK_IN
SYNC_IN
SI
TXD
1
2
3
4
5
6
7
8
9
6
6
6
6
6
6
6
6
3
3
3
3
3
3
2
2
2
4
4
4
4
3
3
3
3
I
D
D
D
D
D
D
S
S
S
S
A
A
S
S
S
S
S
S
S
C
S
S
S
S
S
18
19
17
16
15
14
13
12
11
10
26
25
24
23
22
21
20
52
51
53
54
55
56
57
58
59
60
44
45
46
47
48
49
50
SYNC_IN
RXD
TXD
SCLKX2*
SCLK
RSRVD
FSYNC*
SI_MS
SO_MS
SI_FS
SO_FS
CLK_IN
RESET
I*
MC
SD_15
SD_14
SD_13
SD_12
D_6
D_7
CS*
RD*
WR*
SC2000
68-PIN PLCC
(TOP VIEW)
Physical Pinout
Logical Pin Organization
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