參數(shù)資料
型號: SC2000
廠商: NXP SEMICONDUCTORS
元件分類: 路由/交換
英文描述: Universal Timeslot Interchange
中文描述: TELECOM, DIGITAL TIME SWITCH, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 27/44頁
文件大?。?/td> 221K
代理商: SC2000
2000 Sep 07
27
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Table 7.
Local Bus Interface Timing — PEB Network Module Without Swithing
Symbol
Parameter
Mn
Typ
Max
Unit
t1a
L_CLKT, CLKR high time (1.544 Mbps)
323
ns
t1b
L_CLKT, CLKR high time (2.048 Mbps)
244
ns
t2a
L_CLKT, CLKR low time (1.544 Mbps)
323
ns
t2b
L_CLKT, CLKR low time (2.048 Mbps)
244
ns
t3a
L_CLKT, CLKR period (1.544 Mbps)
647
ns
t3b
L_CLKT, CLKR period (2.048 Mbps)
488
ns
t4
SO_CLK
delay fromL_CLKT
35
ns
t5
SO_CLK
delay fromL_CLKT
35
ns
t6
SO_FS
delay fromL_FSYNCT
35
ns
t7
SO_FS
delay fromL_FSYNCT
35
ns
t8
SO_MS
delay fromL_MSYNCT
35
ns
t9
SO_MS
delay fromL_MSYNCT
35
ns
t10
SO delay fromSERT, L_SERT
35
ns
t11
SO delay fromL_TSX*
35
ns
t12
SI_CLK
delay fromLCLKR
35
ns
t13
SI_CLK
delay fromL_CLKR
35
ns
t14
FSYNCR setup to CLKR
5
ns
t15
FSYNCR hold fromCLKR
15
ns
t16
SI_FS
delay fromFSYNCR
35
ns
t17
SI_FS
delay fromFSYNCR
35
ns
t18
SI_MS
delay fromMSYNCR
35
ns
t19
SI_MS
delay fromMSYNCR
35
ns
t20
SERR enable delay fromCLKR
70
ns
t21
SERR delay fromSI
60
ns
t22
SERR disable delay fromCLKR
70
ns
Note:
1. Timng measured with 100 pF load on all Local Bus outputs, 200 pF 220/330
termnation on all PEB outputs. Open collector low to high transitions
include 43 ns delay fromhi-Z to 2.4 V.
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