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參數(shù)資料
| 型號(hào)： | SC2000 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 路由/交換 |
| 英文描述： | Universal Timeslot Interchange |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 8/44頁 |
| 文件大小： | 221K |
| 代理商： | SC2000 |
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2000 Sep 07
8
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
REGISTER DESCRIPTION
Microprocessor Interface Registers
The four 8-bit Microprocessor Interface
Registers comprise the command and
control port for the SC2000.
Command/Status Register
Busy (CS_0):
This bit is automatically
set to 1 when a command that requires
synchronization with the SC2000’s in-
ternal state machine has been initiated.
The bit is cleared to 0 when the com-
mand has been completed. The follow-
ing commands require synchronization:
Destination Routing Memory Write
Source Routing Memory Write
Parallel Access Destination Write
Parallel Access Source Read
Read (CS_1):
Setting this bit to 1 ini-
tiates a read of the register pointed to
by the contents of the Internal Address
Register. Once the BUSY bit is read as
cleared to 0 the contents of the selected
register will be available in the Low Byte
and High Byte Data Registers. Once the
READ operation is complete the READ
bit is cleared automatically.
Write (CS_2):
Setting this bit to 1 ini-
tiates a write to the register pointed to
by the contents of the Internal Address
Register. Once the busy bit has been
cleared to 0 the contents of the Low Byte
and High Byte Data Registers have been
transferred into the selected register.
Once the WRITE operation is com-
pleted the WRITE bit is cleared auto-
matically.
Terminate (CS_3):
Setting this bit to 1
terminates any command that requires
synchronization with the SC2000’s in-
ternal state machine. This command is
needed to complete a command when
the SC2000’s internal state machine has
stopped running due to the failure of the
system clocks. The command currently
being executed is completed asynchro-
nously and the BUSY bit is cleared to 0.
To restore normal operation the TER-
MINATE bit must be explicitly cleared
to 0. This bit can be read back for verifi-
cation purposes.
Command/Status Register
BIT
R/W
Command/Status
0
R
CS_0: Busy (S)
1
W
CS_1: Read (C)
2
W
CS_2: Write (C)
3
R/W
CS_3: Termnates (C)
4
CS_4: Reserved
5
CS_5: Reserved
6
CS_6: Reserved
7
R/W
CS_7: Reset (C)
Note:
(1) Bit 0 is the LSB of the byte.
(2) Initiating multiple commands in a
single access is not recommended.
CPU Interface Register Map
A_1
A_0
Register Name
0
0
Command/Status
0
1
Internal Address
1
0
Low Byte Data
1
1
High Byte Data
Low Byte Data Register
BIT
R/W
Function
0
R/W
D_0
1
R/W
D_1
2
R/W
D_2
3
R/W
D_3
4
R/W
D_4
5
R/W
D_5
6
R/W
D_6
7
R/W
D_7
Note:
Bit 0 is the LSB of the byte.
High Byte Data Register
BIT
R/W
Function
0
R/W
D_8
1
R/W
D_9
2
R/W
D_10
3
R/W
D_11
4
R/W
D_12
5
R/W
D_13
6
R/W
D_14
7
R/W
D_15
Note:
Bit 0 is the LSB of the byte.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SC2001G-10 | Bus Exchanger |
| SC2001G-13 | Bus Exchanger |
| SC2344 | BJT |
| SC26C94 | Quad universal asynchronous receiver/transmitter QUART |
| SC26C94A1A | Quad universal asynchronous receiver/transmitter QUART |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC20001RM | 制造商:STACO ENERGY PROD CO 功能描述:UPS system, Unistar III, rack, 2kVA, 1.4kW, 120VAC input, 120VAC output |
| SC20001T | 制造商:STACO ENERGY PROD CO 功能描述:UPS system, Unistar III, tower, 2kVA, 1.4kW, 120VAC input, 120VAC output |
| SC-2001 | 制造商:Thomas & Betts 功能描述:SVCE CBL CAP, OVAL W/SPLIT INSUL 制造商:Thomas & Betts 功能描述:Fittings Clamp Steel |
| SC2001-1 | 制造商:Thomas & Betts 功能描述:SVCE CBL CAP, OVAL W/SPLIT INSUL,EA |
| SC2001G-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Bus Exchanger |
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