參數(shù)資料
型號: SC2000
廠商: NXP SEMICONDUCTORS
元件分類: 路由/交換
英文描述: Universal Timeslot Interchange
中文描述: TELECOM, DIGITAL TIME SWITCH, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 36/44頁
文件大?。?/td> 221K
代理商: SC2000
2000 Sep 07
36
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Table 13.
CLK_IN, SYNC_IN — PEB Network Master Mode (CLK_IN Divider
2)
Symbol
Parameter
Mn
Typ
Max
Unit
t1
CLK_IN period
244
ns
t2
CLK_IN high time
122
ns
t3
CLK_IN low time
122
ns
t4
SYNC_IN low setup to CLK_IN
(PEB conventional)
10
ns
t5
SYNC_IN low hold fromCLK_IN
(PEB conventional)
10
ns
t6
SYNC_IN high setup to CLK_IN
(PEB conventional)
10
ns
t7
SYNC_IN high hold fromCLK_IN
(PEB conventional)
10
ns
t8
SYNC_IN setup to CLK_IN
(ST-BUS)
10
ns
t9
SYNC_IN hold fromCLK_IN
(ST-BUS)
10
ns
t10a
CLKR, L_CLKT
delay fromCLK_IN
(PEB conventional)
60
ns
t10b
CLKR, L_CLKT
delay fromCLK_IN
(ST-BUS)
60
ns
t11a
CLKR, L_CLKT
delay fromCLK_IN
(PEB conventional)
30
ns
t11b
CLKR, L_CLKT
delay fromCLK_IN
(ST-BUS)
30
ns
t12
FSYNCR, L_FSYNCT
delay fromCLKR
70
ns
t13
FSYNCR, L_FSYNCT
delay fromCLKR
35
ns
t14
MSYNCR
delay fromCLKR
70
ns
t15
MSYNCR
delay fromCLKR
35
ns
t16
L_MSYNCT
delay fromCLKR
70
ns
t17
L_MSYNCT
delay fromCLKR
35
ns
t18
L_MSYNCT
delay fromMSYNCT
60
ns
t19
L_MSYNCT
delay fromMSYNCT
25
ns
Note:
1. Timng measured with 200 pF 220/330
termnation on all PEB outputs. Open collector low to high transitions include 43 ns delay fromhi-Z to 2.4 V.
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