參數(shù)資料
型號(hào): SC16C752
廠商: NXP Semiconductors N.V.
英文描述: Dual UART with 64-byte FIFO
中文描述: 雙UART具有64字節(jié)FIFO
文件頁數(shù): 34/47頁
文件大?。?/td> 604K
代理商: SC16C752
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
34 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
When in
both
DMA mode 0
and
FIFO enable mode, the write cycle delay should be larger than one x
1
clock cycle.
max
[2]
= 333 ns (for Baudrate
max
= 1.5 Mbits/s)
= 1
μ
s (for Baudrate
max
= 460.8 kbits/s)
= 4
μ
s (for Baudrate
max
= 115.2 kbits/s)
[3]
Applies to external clock; crystal oscillator max 24 MHz.
11.1 Timing diagrams
t
p1
, t
p2
t
p3
t
(RESET)
t
su1
t
su2
t
su3
clock cycle period
clock speed
RESET pulse width
address set-up time
data set-up time
set-up time from IOW or IOR assertion
to XTAL1 clock LOW-to-HIGH transition
IOR strobe width
IOW strobe width
10
-
200
0
16
20
-
48
-
-
-
-
6
-
200
0
16
20
-
80
-
-
-
-
ns
MHz
ns
ns
ns
ns
[3]
t
w1
t
w2
77
30
-
-
30
30
-
-
ns
ns
[2]
Table 26:
T
amb
=
40
°
C to +85
°
C; V
CC
= 2.5 V 3.3 V
±
10% or 5 V
±
10%, unless specified otherwise.
Symbol
Parameter
AC electrical characteristics
…continued
Conditions
2.5 V
3.3 V and 5 V
Min
Unit
Min
Max
Max
IOWstrobe
max
)
--------------------------------------
=
Fig 13. General read timing.
DATA
ACTIVE
ACTIVE
VALID
ADDRESS
002aaa235
tsu1
th4
td1
tw1
td2
td3
td4
A0–A2
CSA,
CSB
IOR
D0–D7
th1
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