參數(shù)資料
型號(hào)： SC16C752
廠商： NXP Semiconductors N.V.
英文描述： Dual UART with 64-byte FIFO
中文描述： 雙UART具有64字節(jié)FIFO
文件頁(yè)數(shù)： 33/47頁(yè)
文件大小： 604K
代理商： SC16C752
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
33 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[3]
These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150
°
C. The customer is
responsible for verifying junction temperature.
These parameters apply for D7-D0.
These parameters apply for DTRA, DTRB, INIA, INTB, RTSA, RTSB, RXRDYA, RXRDYB, TXRDYA, TXRDYB, TXA, TXB.
Measurement condition, normal operation other than sleep mode:
V
CC
= 3.3 V; T
amb
= 25
°
C. Full duplex serial activity on all two serial (UART) channels at the clock frequency specified in the
recommended operating conditions with divisor of 1.
Except x
2
, V
OL
= 1 V typical.
Applies to external clock; crystal oscillator max. 24 MHz.
[4]
[5]
[6]
[7]
[8]
11. Dynamic characteristics
Table 26:
T
amb
=
40
°
C to +85
°
C; V
CC
= 2.5 V 3.3 V
±
10% or 5 V
±
10%, unless specified otherwise.
Symbol
Parameter
AC electrical characteristics
Conditions
2.5 V
3.3 V and 5 V
Min
0
20
-
-
10
25
-
-
-
-
Unit
Min
10
20
-
-
10
25
-
-
-
-
Max
-
-
77
15
-
-
100
100
100
1
Max
-
-
26
15
-
-
33
24
24
1
t
d1
t
d2
t
d3
t
d4
t
d5
t
d6
t
d7
t
d8
t
d9
t
d10
IOR delay from chip select
read cycle delay
delay from IOR to data
data disable time
IOW delay from chip select
write cycle delay
delay from IOW to output
delay to set interrupt from modem input
delay to reset interrupt from IOR
delay from stop to set interrupt
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
clk
baud
rate
ns
ns
R
clk
baud
rate
ns
R
clk
baud
rate
ns
ns
R
clk
baud
rate
ns
25 pF load
25 pF load
25 pF load
[1]
25 pF load
25 pF load
25 pF load
t
d11
t
d12
t
d13
delay from IOR to reset interrupt
delay from start to set interrupt
delay from IOW to transmit start
25 pF load
-
-
8
100
100
24
-
-
8
29
100
24
t
d14
t
d15
delay from IOW to reset interrupt
delay from stop to set RXRDY
-
-
100
1
-
-
70
1
t
d16
t
d17
t
d18
delay from IOR to reset RXRDY
delay from IOW to set TXRDY
delay from start to reset TXRDY
-
-
-
100
100
16
-
-
-
75
70
16
t
d19
delay between successive assertion of
IOW and IOR
chip select hold time from IOR
chip select hold time from IOW
data hold time
address hold time
hold time from XTAL1 clock
HIGH-to-LOW transition to IOW or IOR
release
-
20
-
20
t
h1
t
h2
t
h3
t
h4
t
h5
0
0
15
0
20
-
-
-
-
-
0
0
15
0
20
-
-
-
-
-
ns
ns
ns
ns
ns
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