參數(shù)資料
型號(hào): SC16C752
廠商: NXP Semiconductors N.V.
英文描述: Dual UART with 64-byte FIFO
中文描述: 雙UART具有64字節(jié)FIFO
文件頁(yè)數(shù): 22/47頁(yè)
文件大?。?/td> 604K
代理商: SC16C752
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
22 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.4 Line control register (LCR)
This register controls the data communication format. The word length, number of
stop bits, and parity type are selected by writing the appropriate bits to the LCR.
Table 12
shows the line control register bit settings.
Table 12:
Bit
7
Line Control Register bits description
Symbol
Description
LCR[7]
Divisor latch enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
LCR[6]
Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.
Logic 0 = no TX break condition (normal default condition).
Logic 1 = forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition.
LCR[5]
Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).
Logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1
for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0
for the transmit and receive data.
LCR[4]
Parity type select.
Logic 0 = ODD Parity is generated (if LCR[3] = 1).
Logic 1 = EVEN Parity is generated (if LCR[3] = 1).
LCR[3]
Parity enable.
Logic 0 = no parity (normal default condition).
Logic 1 = a parity bit is generated during transmission and the
receiver checks for received parity.
LCR[2]
Number of Stop bits. Specifies the number of stop bits.
0 - 1 stop bit (word length = 5, 6, 7, 8)
1 - 1.5 stop bits (word length = 5)
1 = 2 stop bits (word length = 6, 7, 8)
LCR[1-0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received.
00 - 5 bits
01 - 6 bits
10 - 7 bits
11 - 8 bits
6
5
4
3
2
1-0
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