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參數(shù)資料
| 型號(hào)： | SC16C752 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual UART with 64-byte FIFO |
| 中文描述： | 雙UART具有64字節(jié)FIFO |
| 文件頁數(shù)： | 28/47頁 |
| 文件大?。?/td> | 604K |
| 代理商： | SC16C752 |
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Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
28 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.11 Divisor latches (DLL, DLH)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud
clock in the baud rate generator. DLH stores the most significant part of the divisor.
DLL stores the least significant part of the divisor.
Note that DLL and DLH can only be written to before sleep mode is enabled, i.e.,
before IER[4] is set.
7.12 Transmission control register (TCR)
This 8-bit register is used to store the RX FIFO threshold levels to stop/start
transmission during hardware/software flow control.
Table 20
shows transmission
control register bit settings.
TCR trigger levels are available from 0-60 bytes with a granularity of four.
Remark:
TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The
programmer must program the TCR such that TCR[3:0] > TCR{7:4]. There is no
built-in hardware check to make sure this condition is met. Also, the TCR must be
programmed with this condition before Auto-RTS or software flow control is enabled
to avoid spurious operation of the device.
7.13 Trigger level register (TLR)
This 8-bit register is pulsed to store the transmit and received FIFO trigger levels
used for DMA and interrupt generation. Trigger levels from 4-60 can be programmed
with a granularity of 4.
Table 21
shows trigger level register bit settings.
Remark:
TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or
TLR[7:4] are logical 0, the selectable trigger levels via the FIFO control register (FCR)
are used for the transmit and receive FIFO trigger levels. Trigger levels from 4-60
bytes are available with a granularity of four. The TLR should be programmed for
N
4
,
where N is the desired trigger level.
When the trigger level setting in TLR is zero, the SC16C752 uses the trigger level
setting defined in FCR. If TLR has non-zero trigger level value, the trigger level
defined in FCR is discarded. This applies to both transmit FIFO and receive FIFO
trigger level setting.
When TLR is used for RX trigger level control, ICR[7:6] should be left at the default
state, i.e., ‘00’.
Table 20:
Bit
7-4
3-0
Transmission Control Register bits description
Symbol
Description
TCR[7:4]
RX FIFO trigger level to
resume
transmission (0-60).
TCR[3:0]
RX FIFO trigger level to
halt
transmission (0-60).
Table 21:
Bit
7-4
3-0
Trigger Level Register bits description
Symbol
Description
TLR[7:4]
RX FIFO trigger levels (4-60), number of characters available.
TLR[3:0]
TX FIFO trigger levels (4-60), number of spaces available.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| SC16C752B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs |
| SC16C752B_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs |
| SC16C752BIB48 | 制造商:NXP Semiconductors 功能描述:IC UART DUAL 64BYTE FIFO 16C752 制造商:NXP Semiconductors 功能描述:IC, UART, DUAL, 64BYTE FIFO, 16C752 制造商:NXP Semiconductors 功能描述:IC, UART, DUAL, 64BYTE FIFO, 16C752, No. of Channels:2, Data Rate:5Mbps, Supply Voltage Min:2.25V, Supply Voltage Max:5.5V, Digital IC Case Style:LQFP, No. of Pins:48, Operating Temperature Min:-40C, Operating Temperature Max:85C, , RoHS Compliant: Yes |
| SC16C752BIB48,128 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C752BIB48,151 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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