參數(shù)資料
型號(hào): SC16C752
廠商: NXP Semiconductors N.V.
英文描述: Dual UART with 64-byte FIFO
中文描述: 雙UART具有64字節(jié)FIFO
文件頁(yè)數(shù): 27/47頁(yè)
文件大?。?/td> 604K
代理商: SC16C752
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
27 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.10 Enhanced feature register (EFR)
This 8-bit register enables or disables the enhanced features of the UART.
Table 19
shows the enhanced feature register bit settings.
Table 18:
Priority
level
1
2
2
3
4
5
Interrupt priority list
IIR[5]
IIR[4]
IIR[3]
IIR[2]
IIR[1]
IIR[0]
Source of the interrupt
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
Receiver Line Status error
Receiver time-out interrupt
RHR interrupt
THR interrupt
Modem interrupt
Received Xoff signal/
special character
CTS, RTS change of state
from active (LOW) to
inactive (HIGH)
6
1
0
0
0
0
0
Table 19:
Bit
7
Enhanced Feature Register bits description
Symbol
Description
EFR[7]
CTS flow control enable.
Logic 0 = CTS flow control is disabled (normal default condition).
Logic 1 = CTS flow control is enabled. Transmission will stop when a
HIGH signal is detected on the CTS pin.
EFR[6]
RTS flow control enable.
Logic 0 = RTS flow control is disabled (normal default condition).
Logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when
the receiver FIFO HALT trigger level TCR[3:0] is reached, and goes
LOW when the receiver FIFO RESUME transmission trigger level
TCR[7:4] is reached.
EFR[5]
Special character detect.
Logic 0 = Special character detect disabled (normal default condition).
Logic 1 = Special character detect enabled. Received data is
compared with Xoff-2 data. If a match occurs, the received data is
transferred to FIFO and IIR[4] is set to a logical 1 to indicate a special
character has been detected.
EFR[4]
Enhanced functions enable bit.
Logic 0 = Disables enhanced functions and writing to IER[7:4],
FCR[5:4], MCR[7:5].
Logic 1 = Enables the enhanced function IER[7:4], FCR[5:4], and
MCR[7:5] can be modified, i.e., this bit is therefore a write enable.
EFR[3:0]
Combinations of software flow control can be selected by programming
these bits. See
Table 3 “Software flow control options (EFR[0:3])” on
page 9
.
6
5
4
3-0
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