參數(shù)資料
型號: SC16C752
廠商: NXP Semiconductors N.V.
英文描述: Dual UART with 64-byte FIFO
中文描述: 雙UART具有64字節(jié)FIFO
文件頁數(shù): 25/47頁
文件大?。?/td> 604K
代理商: SC16C752
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
25 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.7 Modem status register (MSR)
This 8-bit register provides information about the current state of the control lines
from the mode, data set, or peripheral device to the processor. It also indicates when
a control input from the modem changes state.
Table 15
shows modem status
register bit settings per channel.
[1]
The primary inputs RI, CD, CTS, DSR are all Active-LOW, but their registered equivalents in the MSR
and MCR (in loop-back) registers are Active-HIGH.
7.8 Interrupt enable register (IER)
The interrupt enable register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from
LOW to HIGH. The INT output signal is activated in response to interrupt generation.
Table 16
shows interrupt enable register bit settings.
Table 15:
Bit
7
Modem Status Register bits description
Symbol
Description
MSR[7]
CD (Active-HIGH, logical 1). This bit is the complement of the CD input
during normal mode. During internal loop-back mode, it is equivalent to
MCR[3].
MSR[6]
RI (Active-HIGH, logical 1). This bit is the complement of the RI input
during normal mode. During internal loop-back mode, it is equivalent to
MCR[2].
MSR[5]
DSR (Active-HIGH, logical 1). This bit is the complement of the DSR
input during normal mode. During internal loop-back mode, it is
equivalent MCR[0].
MSR[4]
CTS (Active-HIGH, logical 1). This bit is the complement of the CTS
input during normal mode. During internal loop-back mode, it is
equivalent to MCR[1].
MSR[3]
CD. Indicates that CD input (or MCR[3] in loop-back mode) has
changed state. Cleared on a read.
MSR[2]
RI. Indicates that RI input (or MCR[2] in loop-back mode) has changed
state from LOW to HIGH. Cleared on a read.
MSR[1]
DSR. Indicates that DSR input (or MCR[0] in loop-back mode) has
changed state. Cleared on a read.
MSR[0]
CTS. Indicates that CTS input (or MCR[1] in loop-back mode) has
changed state. Cleared on a read.
6
5
4
3
2
1
0
Table 16:
Bit
7
Interrupt Enable Register bits description
Symbol
Description
IER[7]
[1]
CTS interrupt enable.
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt.
IER[6]
[1]
RTS interrupt enable.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt.
IER[5]
[1]
Xoff interrupt.
Logic 0 = Disable the Xoff interrupt (normal default condition).
Logic 1 = Enable the Xoff interrupt.
6
5
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